Renesas 89HPES24T3G2ZBAL, Руководство пользователя

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IDT Configuration Registers
PES24T3G2 User Manual 8 - 34 February 22, 2012
Notes
5 HASD RO 0x0 Hardware Autonomous Speed Disable. When set, this bit pre-
vents hardware from changing the link speed for device specific
reasons other than to correct unreliable link operation by reduc-
ing the link speed. Initial transition to the highest supported com-
mon link speed is not blocked by this bit.
The PES24T3G2 ports do not have an autonomous mechanism
to regulate link speed, except due to link reliability issues. There-
fore, this bit is not applicable to the PES24T3G2 ports.
Note that this bit does not affect link speed changes triggered by
software setting the target link speed and link-retrain bits. Refer
to section Link Speed Negotiation on page 3-4 for further details.
6 SDE RWL 0x0 Selectable De-emphasis. For switch downstream ports, this bit
sets the de-emphasis level when the link operates at 5.0 Gbps.
For the upstream port, this bit selects the de-emphasis prefer-
ence advertised via training sets (the actual de-emphasis on the
link is selected by the link partner).
0x0 - De-emphasis level = -6.0 dB
0x1 - De-emphasis level = -3.5 dB
This bit has no effect when the link operates at 2.5 Gbps, or when
the link operates in low-swing mode.
When this field is modified, the newly selected de-emphasis is
not applied until the PHY LTSSM transitions through the states in
which it is allowed to modify the de-emphasis setting on the line
(i.e., Recovery.Speed). Therefore, after modifying this field, it is
recommended that the link be fully retrained by setting the
FLRET bit in the PHYLSTATE0 register.
9:7 TM RW 0x0
Sticky
Transmit Margin. This field controls the value of the non de-
emphasized voltage level at the transmitter pins. This field is
reset to 0x0 on entry to the LTSSM Polling.Configuration sub-
state.
0x0 - Normal operating range
0x1 - 900 mV for full swing and 500 mV for low-swing
0x2 - 700 mV for full swing and 400 mV for low-swing
0x3 - 500 mV for full swing and 300 mV for low-swing
0x4 - 300 mV for full swing and 200 mv for low-swing
0x5 - 200 mV for full swing and 100 mv for low-swing
0x6-0x7 - Reserved
This register is intended for debug, compliance testing purpose
only. System firmware and software is allowed to modify this reg-
ister only during debug or compliance testing. In all other cases,
the system must ensure that this register is set to the default
value.
When this field is set to “Normal Operating Range”, the SerDes
transmitter drive level is selected via the SerDes Global Transmit-
ter Control register (STXGCTL) and SerDes Transmitter Lane
Control register (STXLCTL).
When this field is modified, the newly selected value is not
applied until the PHY LTSSM transitions through the states in
which it is allowed to modify the transmit margin setting on the
line (i.e., Recovery.RcvrLock). Therefore, after modifying this
field, it is recommended that the link be retrained by setting the
LRET bit in the PCIELCTL register.
Bit
Field
Field
Name
Type
Default
Value
Description