Renesas 89HPES24T3G2ZBAL, Руководство пользователя

Страница: 108 / 165

IDT Configuration Registers
PES24T3G2 User Manual 8 - 26 February 22, 2012
Notes
5 LRET RW 0x0 Link Retrain. Writing a one to this field initiates Link retraining by
directing the Physical Layer LTSSM to the Recovery state. This
field always returns zero when read.
It is permitted to set this bit while simultaneously modifying other
fields in this register.
When this bit is set and the LTSSM is already in the Recovery or
Configuration states, all modifications that affect link retraining
are applied in the subsequent retraining. Else, if the LTSSM is
not in the Recovery or Configuration states, modifications that
affect link retraining are applied immediately.
For compliance with the PCIe specification, this bit has no effect
on the upstream port when the REGUNLOCK bit is cleared in the
SWCTL register. In this mode the field is hardwired to zero. When
the REGUNLOCK bit is set, writing a one to the LRET bit initiates
link retraining on the upstream port with a delayed effect of 1 ms.
For the upstream port, the effect of setting the LRET bit is
delayed by 1ms to allow the completion associated with the con-
figuration access that set the bit to be sent towards the root.
Therefore, for the upstream port, software must wait 1ms after
setting the LRET bit before polling the RLWS field.
Setting LRET in the upstream port does not result in the immedi-
ate setting of the LTRAIN bit in the PCIELSTS register. The
LTRAIN bit is set at a 1ms delay.
6 CCLK RW 0x0 Common Clock Configuration. When set, this bit indicates that
this component and the component at the opposite end of the link
are operating with a distributed common reference clock.
7 ESYNC RW 0x0 Extended Sync. When set this bit forces transmission of addi-
tional ordered sets when exiting the L0s state and when in the
recovery state.
8 CLKP-
WRMGT
RO 0x0 Enable Clock Power Management. The PES24T3G2 does not
support this feature.
9 HAWD RO 0x0 Hardware Autonomous Width Disable. When set, this bit disables
hardware from changing the link width for reasons other than
attempting to correct for unreliable link operation by reducing the
link width.
The PES24T3G2 ports do not have a hardware autonomous
mechanism to change link width, except due to link reliability
issues. Therefore, this bit is not applicable and is hardwired to
zero.
10 LBWINTEN RW 0x0 Link Bandwidth Management Interrupt Enable. When set, this
bit enables the generation of an interrupt to indicate that the
LBWSTS bit has been set in the PCIELSTS register.
If the LBN field in the PCIELCAP register is cleared, this field is
hardwired to zero.
This field is hardwired to zero in the upstream port.
11 LABWINTEN RW 0x0 Link Autonomous Bandwidth Interrupt Enable. When set, this
bit enables the generation of an interrupt to indicate that the
LABWSTS bit has been set in the PCIELSTS register.
If the LBN field in the PCIELCAP register is cleared, this field is
hardwired to zero.
This field is hardwired to zero in the upstream port.
Bit
Field
Field
Name
Type Default
Value
Description