Renesas 89HPES24T3G2ZBAL, Руководство пользователя

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IDT Link Operation
PES24T3G2 User Manual 3 - 3 February 22, 2012
Notes
The Maximum Link Width (MAXLNKWDTH) field in a port’s PCI Express Link Capabilities (PCIELCAP)
register contains the maximum link width of the port. This field is of RWL type and may be modified when
the REGUNLOCK bit is set in the SWCTL register. Modification of this field allows the maximum link width
of the port to be configured. The new link width takes effect the next time full link training occurs.
To force a link width to a smaller width than the default value, the MAXLNKWDTH field could be config-
ured through Serial EEPROM initialization and full link retraining forced by setting the Full Link Retrain
(FLRET) bit in the PHYLSTATE0 register. The value programmed into the MAXLNKWDTH field should not
exceed the port’s width (x4 for the PES24T3G2). When the MAXLNKWDTH field of a port’s PCIELCAP
register is configured to a value higher than the port’s supported link width, the port operates at its default
link width (i.e., default value of MAXLNKWDTH). For example, a port which is initially set to x4 Gen2 must
not have the value of the MAXLNKWDTH programmed to x8. If the MAXLNKWDTH field were to be incor-
rectly programmed to x8, the port would operate at x4.
When a port is disabled, all SerDes lanes associated with that port are turned off. Unused lanes associ-
ated with a x4 port are put into a low power state. When only four lanes associated with a x8 port are used,
the upper four lanes are turned off. When fewer than four lanes associated with a x8 port are used, the
upper four lanes are turned off and the unused lower lanes are put into a low power state.
Dynamic Link Width Reconfiguration
The PCI Express 2.0 specification includes support for dynamic upconfiguration of link widths. This
optional capability allows both components of a link to dynamically downconfigure and upconfigure links
based on implementation specific criteria such as power savings, link bandwidth requirements, or link reli-
ability problems. As an example, a link that initially does a full link train to x4 may be dynamically downcon-
figured to x1 in order to save power when there is little traffic on the link. As traffic increases, the link may be
dynamically upconfigured to its initial link width of x4. Also, the link width may be downconfigured if a partic-
ular lane is determined to be unreliable.
With dynamic link width upconfiguration, the system designer can choose to connect components with
enough lanes to handle worst case bandwidth requirements, yet not waste power when the link is not fully
utilized. This capability offers an additional mechanism for link power reduction on top of the traditional
ASPM link states (L0s, L1, etc.).
Dynamic upconfiguration and downconfiguration is done on a per-link basis, and does not result in the
link going into a DL_Down state. A link can be upconfigured up to the negotiated link width set after a full
link train. For example, a link that trained to a width of x2 after a full link train cannot be upconfigured to a
width above x2. A link can be downconfigured down to x1. When a link is downconfigured to a smaller
width, inactive lanes are kept in Electrical Idle with their receiver terminations enabled. These lanes
continue to be associated with the downconfigured port’s LTSSM.
In order for upconfiguration to occur successfully, both of the link components must support it. Further-
more, the PCIe specification recommends that a link component not initiate downconfiguration unless the
link partner supports link upconfiguration, except for link reliability reasons. The capability to upconfigure a
link is transmitted among components using the in-band TS2 ordered set.
When downconfiguration or upconfiguration of a link occurs, one of the components on the link initiates
the process, while the other component responds to the process. The PCIe specification indicates that both
of these capabilities are optional. Software may be notified of link width re-configuration via the link band-
width notification mechanism described in the PCIe 2.0 specification. This mechanism is enabled by setting
the Link Bandwidth Management Interrupt Enable (LBWINTEN) bit in the PCIELCTL register of switch
downstream ports.
Dynamic Link Width Reconfiguration Support in the PES24T3G2
The PES24T3G2 supports dynamic link width upconfiguration and downconfiguration in response to link
partner requests.