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IDT   Link Operation

PES24T3G2 User Manual

3 - 5

February 22, 2012

Notes

Note that in this case the Link Bandwidth Management Status (LBWSTS) bit in the PCIELSTS register

of the downstream port is not set, since the initial link speed upgrade was not caused by a software directed
link retrain or by link reliability issues. The same behavior applies after full link retrain (i.e., when the LTSSM
transitions through the ‘Detect’ state). The current link speed of each port is reported via the Current Link
Speed (CLS) field of the port’s Link Status Register (PCIELSTS).

When a link speed upgrade operation fails, the PHY LTSSM reverts back to the speed before the

upgrade (i.e., 2.5 Gbps) and does not autonomously initiate a subsequent link speed upgrade. The PHY
continues to respond to link partner requests for link speed upgrade or to link speed upgrades triggered by
the software setting the Link Retrain (LRET) bit in the PCIELCTL register.

The PES24T3G2 ports do not autonomously change speed. As a result, the PES24T3G2 ports never

set the ‘Autonomous Change’ bit in the training sets exchanged with the link partner during link training.
Still, a link partner connected to a PES24T3G2 downstream port may autonomously change link speed.
When this occurs, the PES24T3G2 downstream port sets the Link Autonomous Bandwidth Status
(LABWSTS) bit in the PCIELSTS register. A system designer may limit the maximum speed at which each
port operates by changing the target link speed via software or EEPROM and forcing link retraining. Refer
to section Software Management of Link Speed below for further details.

Software Management of Link Speed

Software can interact with the link control and status registers of each port to set the link speed and

receive notification of link speed changes. This gives software the capability to choose the desired link
speed based on system specific criteria. For example, depending on the traffic load expected on a link, soft-
ware can choose to downgrade link speed to 2.5 Gbps in order to reduce power on a low-traffic link and
later upgrade the link to 5.0 Gbps when the bandwidth is required. Software may also choose to change the
link speed due to link reliability reasons (i.e., a link that has reliability problems at 5.0 Gbps may be down-
graded to 2.5 Gbps).

As mentioned above, the Target Link Speed (TLS) field of the Link Control 2 Register (PCIELCTL2) sets

the preferred link speed. By default, the Target Link Speed of each port is set to 5.0 Gbps. 

In order to change link speed, software must write to the TLS field of the port’s PCIELCTL2 register and

subsequently force a link retrain by writing to the Link Retrain (LRET) bit of the Link Control (PCIELCTL)
register. Software is notified of link speed changes via the link bandwidth notification mechanism described
in the PCIe specification. This mechanism is enabled by setting the Link Bandwidth Management Interrupt
Enable (LBWINTEN) bit in the PCIELCTL register of switch downstream ports.

When the link speed is changed (i.e., due to reliability reasons or by virtue of software setting the TLS

field and retraining the link), the downstream port’s LTSSM sets the Link Bandwidth Management Status
(LBWSTS) bit in the PCIELSTS register. Software can verify the link speed by reading the Current Link
Speed (CLS) field of the port’s Link Status Register (PCIELSTS). Note that to force link speed to a value
other than the default value, the TLS field could be configured through Serial EEPROM initialization and full
link retraining forced. Finally, note that the Hardware Autonomous Speed Disable (HASD) bit has no effect
on link speed changes triggered by modifications of the TLS field followed by setting the LRET bit.

Link Reliability

An unreliable link is a link that exhibits recurrent errors detected in the physical layer. These errors

include bit-flipping due to electrical problems, SerDes transmitter and receiver problems, lack of synchroni-
zation between transmitter and receiver, etc. All of these usually result in LCRC failures at the data-link
layer. In severe cases, link reliability problems cause the link to be automatically retrained (refer to section
Link Retraining on page 3-7). As the link speed increases (i.e., Gen2 in PCI Express 2.0), the link is more
susceptible to link errors due to tighter margins in the data window. 

1. 

Initial link speed upgrade is not considered an autonomous link speed upgrade, since it is caused by the default 

setting of the Target Link Speed field in the PCIELCTL2 register. 

Содержание 89HPES24T3G2ZBAL

Страница 1: ...2 6024 Silver Creek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2012 Integrated Device Technology Inc IDT 89HPES24T3G2 PCI Express Switc...

Страница 2: ...PLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPE...

Страница 3: ...ts or alternate functions Chapter 5 SMBus Interfaces describes the operation of the 2 SMBus interfaces on the PES24T3G2 Chapter 6 Power Management describes the power management capability structure l...

Страница 4: ...x 1 D ABC x 2 D ABCyD Data Units The following data unit terminology is used in this document In quadwords bit 63 is always the most significant bit and bit 0 is the least significant bit In double w...

Страница 5: ...d Write RCW Software can read the register bits with this attribute Reading the value will automatically cause the register bits to be reset to zero Writes cause the register bits to be modified Reser...

Страница 6: ...added text explaining legacy compatibility with Gen1 PCIe switches In Chapter 8 modified the following fields L0SEL in PCIELCAP has default value of 0x6 ARIS in PCIEDCAP2 is RO and ARIFEN in PCIEDCTL2...

Страница 7: ...In Chapter 3 revised section Dynamic Link Width Reconfiguration Support in the PES24T3G2 Also deleted entire section Software Management of Link Width Upconfiguration and Down configuration September...

Страница 8: ...IDT PES24T3G2 User Manual 6 February 22 2012 Notes...

Страница 9: ...1 10 Port Configuration 1 11 Clocking Reset and Initialization Clocking 2 1 Initialization 2 1 Reset 2 2 Fundamental Reset 2 2 Hot Reset 2 5 Upstream Secondary Bus Reset 2 6 Downstream Secondary Bus R...

Страница 10: ...aces Introduction 5 1 Master SMBus Interface 5 2 Initialization 5 2 Serial EEPROM 5 2 I O Expanders 5 7 Slave SMBus Interface 5 12 Initialization 5 13 SMBus Transactions 5 13 Power Management Introduc...

Страница 11: ...Express Virtual Channel Capability 8 49 Power Budgeting Enhanced Capability 8 55 Switch Control and Status Registers 8 56 Autonomous Link Reliability Management 8 71 JTAG Boundary Scan Introduction 9...

Страница 12: ...IDT Table of Contents PES24T3G2 User Manual iv February 22 2012 Notes...

Страница 13: ...8 Table 5 6 I O Expander 0 Signals 5 11 Table 5 7 I O Expander 2 Signals 5 11 Table 5 8 I O Expander 4 Signals 5 12 Table 5 9 Slave SMBus Address When a Static Address is Selected 5 13 Table 5 10 Sla...

Страница 14: ...IDT List of Tables PES24T3G2 User Manual vi February 22 2012 Notes...

Страница 15: ...6 Figure 5 8 CSR Register Read Using SMBus Block Write Read Transactions with PEC Disabled 5 17 Figure 5 9 Serial EEPROM Read Using SMBus Block Write Read Transactions with PEC Disabled 5 17 Figure 5...

Страница 16: ...IDT List of Figures PES24T3G2 User Manual viii February 22 2012 Notes...

Страница 17: ...ication Register 0x002 8 10 ECFGADDR Extended Configuration Space Access Address 0x0F8 8 39 ECFGDATA Extended Configuration Space Access Data 0x0FC 8 40 EEPROMINTF Serial EEPROM Interface 0x42C 8 64 E...

Страница 18: ...tate 0 0x540 8 70 PHYLSTS0 Phy Link Status 0 0x538 8 69 PHYPRBS Phy PRBS Seed 0x55C 8 71 PLTIMER Primary Latency Timer 0x00D 8 13 PMBASE Prefetchable Memory Base Register 0x024 8 16 PMBASEU Prefetchab...

Страница 19: ...rce 0 Capability 0x210 8 51 VCR0CTL VC Resource 0 Control 0x214 8 51 VCR0STS VC Resource 0 Status 0x218 8 52 VCR0TBL0 VC Resource 0 Arbitration Table Entry 0 0x220 8 53 VCR0TBL1 VC Resource 0 Arbitrat...

Страница 20: ...IDT Register List PES24T3G2 User Manual xii February 22 2012 Notes...

Страница 21: ...ignal for hot plug event notification allowing SCI SMI generation for legacy operating systems Dynamic link width reconfiguration for power performance optimization Configurable downstream port PCI to...

Страница 22: ...Unused SerDes are disabled Testability and Debug Features Per port link up and activity status outputs available on I O expander outputs Built in SerDes 8 bit and 10 bit pseudo random bit stream PRBS...

Страница 23: ...Interface Output Replay Buffer TDM Demux Route Map Table Ingress Processor TLP Checker Egress Processor Completion Processor Message Processor TLP Generator Hot Plug Controller Application Layer Data...

Страница 24: ...4 Master SMBus Interface Slave SMBus Interface CCLKUS RSTHALT System Pins JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N JTAG Pins VSS SWMODE 2 0 3 CCLKDS PERSTN REFCLKM MSMBSMODE PE0RP 0 PE0RN 0 PE0RP 7 PE0...

Страница 25: ...efault configuration the Subsystem ID and Subsystem Vendor ID capability structure is not enabled To enable the capability the SSID and SSVID fields in the Subsystem ID and Subsystem Vendor ID SSIDSSV...

Страница 26: ...receive pairs for port 4 PE4TP 7 0 PE4TN 7 0 O PCI Express Port 4 Serial Data Transmit Differential PCI Express trans mit pairs for port 4 PEREFCLKP PEREFCLKN I PCI Express Reference Clock Differenti...

Страница 27: ...4 5 6 are not available in the 19mm package I O General Purpose I O This pin can be configured as a general purpose I O pin Alternate function pin name IOEXPINTN1 Alternate function pin type Input Al...

Страница 28: ...amental reset RSTHALT2 2 RSTHALT is not available in the 19mm package I Reset Halt When this signal is asserted during a PCI Express fundamental reset PES24T3G2 executes the reset procedure and remain...

Страница 29: ...is tor should be connected from these pins to ground REFRES2 REFRES3 I O Port 2 External Reference Resistors Provides a reference for the Port 2 SerDes bias currents and PLL calibration circuitry A 3...

Страница 30: ...al2 Serial Link PE0RP 7 0 I PE0TN 7 0 O PE0TP 7 0 O PE2RN 7 0 I PE2RP 7 0 I PE2TN 7 0 O PE2TP 7 0 O PE4RN 7 0 I PE4RP 7 0 I PE4TN 7 0 O PE4TP 7 0 O PEREFCLKN I HCSL Diff Clock Input Refer to Table 9 i...

Страница 31: ...values under typical operating conditions are 92K for pull up and 90K for pull down 2 All receiver pins set the DC common mode voltage to ground All transmitters must be AC coupled to the media 3 REF...

Страница 32: ...IDT PES24T3G2 Device Overview PES24T3G2 User Manual 1 12 February 22 2012 Notes...

Страница 33: ...s for more informa tion on the serial EEPROM The external serial EEPROM and slave SMBus interface may be used to override the function of some of the signals in the boot configuration vector during a...

Страница 34: ...he assertion of the PCI Express Reset PERSTN input pin A warm reset initiated by the assertion of the PCI Express Reset PERSTN input pin while power is on A warm reset initiated by the writing of a on...

Страница 35: ...3 1 pins is used 10 The master SMBus is taken out of reset and initialized 11 If the selected switch operating mode is one that requires initialization from the serial EEPROM then the contents of the...

Страница 36: ...ed as a GPIO alternate function When a Fundamental Reset occurs all of the GPIO pins default to GPIO inputs Therefore the downstream port resets are tri stated A system designer should use a pull down...

Страница 37: ...progress proceed to step 6 5 The PCI Express stacks and associated logic are held in a quasi reset state in which the following actions occur All links enter an active link training state within 20ms...

Страница 38: ...When an Upstream Secondary Bus Reset occurs the following sequence is executed 1 Each downstream port whose link is up propagates the reset by transmitting TS1 ordered sets with the hot reset bit set...

Страница 39: ...the minimum PxRSTN assertion pulse width is no less than 200 s Downstream port reset outputs can be configured to operate in one of two modes These modes are power enable controlled reset output and...

Страница 40: ...N signal and the negation of the PxRSTN signal is controlled by the value in the Slot Power to Reset Negation PWR2RST field in the HPCFGCTL register When slot power is disabled by writing a one to the...

Страница 41: ...ersion is a function of the receiver and not the transmitter The transmitter never inverts its data During link training the receiver examines symbols 6 through 15 of the TS1 and TS2 ordered sets for...

Страница 42: ...Port without lane reversal PExRP 0 PExRP 1 PExRP 2 PExRP 3 PExRP 4 PExRP 5 PExRP 6 PExRP 7 PES24T3G2 lane 7 lane 6 lane 5 lane 4 lane 3 lane 2 lane 1 lane 0 b x8 Port with lane reversal PExRP 0 PExRP...

Страница 43: ...d to x1 in order to save power when there is little traffic on the link As traffic increases the link may be dynamically upconfigured to its initial link width of x4 Also the link width may be downcon...

Страница 44: ...t is mandatory Also a component may advertise supported link speeds via the Recovery state without necessarily changing the link speed If neither component in the link advertises support for Gen2 then...

Страница 45: ...change the link speed due to link reliability reasons i e a link that has reliability problems at 5 0 Gbps may be down graded to 2 5 Gbps As mentioned above the Target Link Speed TLS field of the Link...

Страница 46: ...nabled until the user clears the EN bit By default the ALR mechanism is disabled When enabled the Autonomous Link Reliability logic monitors the rate of errors in the link When the rate of errors cros...

Страница 47: ...Ie 2 0 specification link retraining can be done autonomously in response to link problems i e repeated TLP replay attempts or as a result of software setting the link retrain LRET bit in the PCI Expr...

Страница 48: ...device or switch Upstream Port When a Set_Slot_Power_Limit message is received by the upstream switch port then the fields in the message are written to the PCI Express Device Capabilities PCIEDCAP r...

Страница 49: ...s to transmit on the upstream port or there are no available flow control credits to transmit a TLP There are no DLLPs pending for transmission on the upstream port The downstream switch ports have th...

Страница 50: ...witch upstream port or endpoint advertises its desired de emphasis by transmission of training sets The upstream compo nent of the link i e switch downstream port or root complex port notes its link p...

Страница 51: ...puts since an incorrect configuration could cause damage to external components as well as the PES24T3G2 GPIO Configuration Associated with each GPIO pin is a bit in the GPIOFUNC GPIOCFG and GPIOD reg...

Страница 52: ...gister is driven on the pin System designers should treat the GPIO outputs as asynchronous outputs The actual value of the output pin can be determined by reading the GPIOD register GPIO Pin Configure...

Страница 53: ...ADDR and SSMBADDR address pins are not available in the 19mm package The MSMBADDR address is hardwired to 0x50 and the SSMBADDR address is hardwired to 0x77 As shown in Figure 5 1 the master and slave...

Страница 54: ...PROM loading occurs if the Switch Mode SWMODE 2 0 field selects an operating mode that performs serial EEPROM initialization The address used by the SMBus interface to access the serial EEPROM is spec...

Страница 55: ...serial EEPROMs See section Programming the Serial EEPROM on page 5 6 for information on in system initialization of the serial EEPROM All register initialization performed by the serial EEPROM is per...

Страница 56: ...tion Sequence Format The final type of configuration block is the configuration done sequence which is used to signify the end of a serial EEPROM initialization sequence If during serial EEPROM initia...

Страница 57: ...rom an uninitialized serial EEPROM will result in a checksum mismatch The checksum is computed in the following manner An 8 bit counter is initialized to zero and the 8 bit sum is computed over the co...

Страница 58: ...busy then the read operation may be initiated by performing a write to the Data DATA field When the serial EEPROM read operation completes the Done DONE bit in the EEPROMINTF register is set and the b...

Страница 59: ...sed in that system configuration should be written to the corresponding IO Expander Address IOE 0 2 4 ADDR field Hot plug outputs and I O expanders may be initialized via serial EEPROM Since the I O e...

Страница 60: ...eight I O expander bits i e I O 1 0 through I O 1 7 The following I O expander configuration sequence is issued by the PES24T3G2 to I O two i e the one that contain hot plug signals and power good in...

Страница 61: ...her on the board and connected to GPIO 2 Whenever IOEXPINTN0 is asserted the PES24T3G2 reads the state of all I O expanders For compatibility with legacy Gen 1 PCIe switches the PES24T3G2 supports ind...

Страница 62: ...issue is with the interrupt logic The IO Expander Test Mode IOEXTM bit in the IOEXPTINF register allows an I O expander test mode to be entered When this bit is set the PES24T3G2 core logic outputs ar...

Страница 63: ...rt 2 electromechanical interlock 8 I O 1 0 I P4APN Port 4 attention push button input 9 I O 1 1 I P4PDN Port 4 presence detect input 10 I O 1 2 I P4PFN Port 4 power fault input 11 I O 1 3 I P4MRLN Por...

Страница 64: ...rt x I O pin y SMBus I O Expander Bit Type Signal Description 0 I O 0 0 1 1 I O x y corresponds to the notation used for PCA9555 port x I O pin y O P0LINKUPN Port 0 link up status output 1 I O 0 1 Unu...

Страница 65: ...d results Associated with each of the above transactions is a command code The command code format for operations supported by the slave SMBus interface is shown in Figure 5 5 and described in Table 5...

Страница 66: ...whether packet error checking is enabled for the cur rent SMBus transaction 0 Packet error checking disabled for the current SMBus transaction 1 Packet error checking enabled for the current SMBus tra...

Страница 67: ...ncodes the CSR operation to be performed 0 CSR write 1 CSR read 5 0 0 Reserved Must be zero 6 RERR Read Only and Clear Read Error This bit is set if the last CSR read SMBus transaction was not claimed...

Страница 68: ...EEPROMINTF register When this bit is set the serial EEPROM SMBus address specified in the EEADDR is used instead of that specified in the MSMBADDR field in the SMBUSSTS register 2 Reserved Reserved 3...

Страница 69: ...erved Must be zero 1 See Table Table 2 in the About This Manual chapter for a definition of these abbreviations Bit Field Name Type1 Description Table 5 14 Serial EEPROM Read or Write CMD Field Descri...

Страница 70: ...BYTCNT 7 A CMD write A ADDRL A ADDRU A CCODE START END DATALL A DATALM A DATAUM A DATAUU A P S PES24T3G2 Slave SMBus Address Wr A CCODE START END N P PES24T3G2 busy with previous command not ready fo...

Страница 71: ...Word S PES24T3G2 Slave SMBus Address Rd DATALM DATALL A N P P S PES24T3G2 Slave SMBus Address Wr A A ADDRU A CCODE END Byte P A S PES24T3G2 Slave SMBus Address Wr A CCODE Byte A P A S PES24T3G2 Slave...

Страница 72: ...IDT SMBus Interfaces PES24T3G2 User Manual 5 20 February 22 2012 Notes...

Страница 73: ...he entire device When the upstream port enters a low power state and the PME_TO_Ack messages are received then the entire device is placed into a low power state The PES24T3G2 supports the following d...

Страница 74: ...is includes both the case when the downstream port is in the D3hot state or the entire switch is in the D3hot state The generation of a PME message by downstream ports necessitates the implementation...

Страница 75: ...ort that does not receive a PME_TO_Ack message in the time out period specified in the PME_TO_Ack Time Out PMETOATO field in its corresponding PME_TO_Ack Timer PMETOATIMER register declares a time out...

Страница 76: ...IDT Power Management PES24T3G2 User Manual 6 4 February 22 2012 Notes...

Страница 77: ...upstream port serves as the add in card s PCIe interface In this application the upstream port may be hot plugged into a slot on the main system Finally Figure 7 3 illustrates the use of the PES24T3G...

Страница 78: ...ot is implemented or on the add in board When located on the add in board state changes are communicated between the hot plug controller asso ciated with the slot and the add in card via hot plug mess...

Страница 79: ...detect The Presence Detect Control PDETECT field in the Hot Plug Configuration Control HPCFGCTL register may be used to control the mechanism used for presence detect Since the polarity of hot plug s...

Страница 80: ...re train the link starting from the Detect state When this occurs the Hot Plug controller for the port does not set the Presence Detect Changed PDC bit in the PCIESSTS register Hot Plug I O Expander T...

Страница 81: ...hot plug event through assertion of the GPEN signal the corresponding port s status bit in the General Purpose Event Status P0_GPESTS register is set A bit in the P0_GPESTS register can only be set i...

Страница 82: ...summary the PES24T3G2 meets all of the I O requirements necessary to build a PICMG compliant hot swap board or system The hot swap I O buffers of the PES24T3G2 may also be used to construct proprietar...

Страница 83: ...ry errors Since memory error reporting via interrupts is an optional capability the MSI capability structure associated with the upstream port is not by default part of the PCI capability structure li...

Страница 84: ...Class Code Register 0x009 on page 8 12 0x00C Byte P0_CLS CLS Cache Line Size Register 0x00C on page 8 13 0x00D Byte P0_PLTIMER PLTIMER Primary Latency Timer 0x00D on page 8 13 Table 8 2 Upstream Port...

Страница 85: ...2C DWord P0_PMLIMITU PMLIMITU Prefetchable Memory Limit Upper Register 0x02C on page 8 17 0x030 Word P0_IOBASEU IOBASEU I O Base Upper Register 0x030 on page 8 17 0x032 Word P0_IOLIMITU IOLIMITU I O L...

Страница 86: ...on page 8 39 0x0F8 Dword P0_ECFGADDR ECFGADDR Extended Configuration Space Access Address 0x0F8 on page 8 39 0x0FC Dword P0_ECFGDATA ECFGDATA Extended Configuration Space Access Data 0x0FC on page 8 4...

Страница 87: ...0 Arbitration Table Entry 3 0x22C on page 8 54 0x280 Dword P0_PWRBCAP PWRBCAP Power Budgeting Capabilities 0x280 on page 8 55 0x284 Dword P0_PWRBDSEL PWRBDSEL Power Budgeting Data Select 0x284 on page...

Страница 88: ...ge 8 67 0x530 Dword P0_PHYLCFG0 PHYLCFG0 Phy Link Configuration 0 0x530 on page 8 68 0x538 Dword P0_PHYLSTS0 PHYLSTS0 Phy Link Status 0 0x538 on page 8 69 0x540 Dword P0_PHYLSTATE0 PHYLSTATE0 Phy Link...

Страница 89: ...Prefetchable Memory Limit Register 0x026 on page 8 17 0x028 DWord Px_PMBASEU PMBASEU Prefetchable Memory Base Upper Register 0x028 on page 8 17 0x02C DWord Px_PMLIMITU PMLIMITU Prefetchable Memory Li...

Страница 90: ...8 37 0x0D0 DWord Px_MSICAP MSICAP Message Signaled Interrupt Capability and Control 0x0D0 on page 8 37 0x0D4 DWord Px_MSIADDR MSIADDR Message Signaled Interrupt Address 0x0D4 on page 8 38 0x0D8 DWord...

Страница 91: ...Capability 0x210 on page 8 51 0x214 DWord Px_VCR0CTL VCR0CTL VC Resource 0 Control 0x214 on page 8 51 0x218 DWord Px_VCR0STS VCR0STS VC Resource 0 Status 0x218 on page 8 52 0x280 Dword Px_PWRBCAP PWR...

Страница 92: ...onomous Link Reliability Status 0x564 on page 8 72 0x568 Dword Px_ALRERT ALRERT Autonomous Link Reliability Error Rate Threshold 0x5680 on page 8 72 0x56C Dword Px_ALRCNT ALRCNT Autonomous Link Reliab...

Страница 93: ...rity Error Enable Not applicable 7 ADSTEP RO 0x0 Address Data Stepping Not applicable 8 SERRE RW 0x0 SERR Enable Non fatal and fatal errors detected by the bridge are reported to the Root Complex when...

Страница 94: ...able 10 9 DEVT RO 0x0 DEVSEL TIming Not applicable 11 STAS RO 0x0 Signalled Target Abort Not applicable since a target abort is never signalled 12 RTAS RO 0x0 Received Target Abort Not applicable 13 R...

Страница 95: ...is field has no effect on the bridge s func tionality but may be read and written by software This field is implemented for compatibility with legacy software Bit Field Field Name Type Default Value D...

Страница 96: ...ch the primary interface of the bridge is connected This field has no functional effect within the PES24T3G2 but is implemented as a read write register for software compatibility Bit Field Field Name...

Страница 97: ...ing This bit always reflects the value of the IOCAP field in the IOBASE register 3 1 Reserved RO 0x0 Reserved field 7 4 IOLIMIT RW 0x0 I O Limit The IOBASE and IOLIMIT registers are used to control th...

Страница 98: ...IT RW 0x0 Memory Address Limit The MBASE and MLIMIT registers are used to control the forwarding of non prefetchable transactions between the primary and secondary interfaces of the bridge This field...

Страница 99: ...field contains A 31 20 of the highest memory address with A 19 0 assumed to be 0xF_FFFF that is below the primary interface of the bridge PMLIMITU specifies the remaining bits Bit Field Field Name Typ...

Страница 100: ...o Bit Field Field Name Type Default Value Description 7 0 CAPPTR RWL 0x40 Capabilities Pointer This field specifies a pointer to the head of the capabilities structure Bit Field Field Name Type Defaul...

Страница 101: ...x0 System Error Enable This bit controls forwarding of ERR_COR ERR_NONFATAL ERR_FATAL from the secondary interface of the bridge to the primary interface Note that error reporting must be enabled in t...

Страница 102: ...equired to update port status 15 7 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 7 0 CAPID RO 0x10 Capability ID The value of 0x10 identifies this capability as a...

Страница 103: ...t an endpoint can withstand due to transition from the L1 state to the L0 state The value is hardwired to 0x0 as this field does not apply to a switch 12 ABP RO 0x0 Attention Button Present In PCIe ba...

Страница 104: ...plicable to the switch since the switch never sets the relaxed ordering bit in transactions it initiates as a requester Therefore this bit is hardwired to 0x0 7 5 MPS RW 0x0 Max Payload Size This fiel...

Страница 105: ...it indicates the status of cor rectable errors Errors are logged in this register regardless of whether error reporting is enabled or not 1 NFED RW1C 0x0 Non Fatal Error Detected This bit indicates th...

Страница 106: ...L0s and L1 are supported 14 12 L0SEL RWL 0x6 L0s Exit Latency This field indicates the L0s exit latency for the given PCI Express link 17 15 L1EL RWL 0x2 L1 Exit Latency This field indicates the L1 e...

Страница 107: ...Type Default Value Description 1 0 ASPM RW 0x0 Active State Power Management ASPM Control This field controls the level of ASPM supported by the link The initial value corresponds to disabled The valu...

Страница 108: ...ister The LTRAIN bit is set at a 1ms delay 6 CCLK RW 0x0 Common Clock Configuration When set this bit indicates that this component and the component at the opposite end of the link are operating with...

Страница 109: ...nk is unable to train the value in this field is set to 0x0 10 TERR RO 0x0 Training Error In PCIe base 1 0a when set this bit indicates that a link training error has occurred The value of this field...

Страница 110: ...wired to zero This field is hardwired to zero in the upstream port 15 LABWSTS RW1C 0x0 Link Autonomous Bandwidth Status This bit is set to indicate that either that the PHY has autonomously changed li...

Страница 111: ...is written or when the link transitions from a non DL_Up status to a DL_Up status This bit is read only and has a value of zero when the SLOT bit in the PCIECAP register is cleared 16 15 SPLS RW 0x0...

Страница 112: ...ected Changed Enable This bit when set enables the generation of a Hot Plug interrupt or wake up event on a presence detect change event This bit is read only and has a value of zero when the corre sp...

Страница 113: ...n Power on 0x1 off Power off 11 EIC RW 0x0 Electromechanical Interlock Control This field always returns a value of zero when read If an electromechanical interlock is implemented a write of a one to...

Страница 114: ...ort and reflects the state of the Presence Detect status 0x0 empty Slot empty 0x1 present Card present 7 EIS RO 0x0 Electromechanical Interlock Status When an electromechani cal interlock is implement...

Страница 115: ...eld Field Name Type Default Value Description 15 0 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 31 0 Reserved RO 0x0 Reserved field Bit Field Field Name Type Defa...

Страница 116: ...ify the de emphasis setting on the line i e Recovery Speed Therefore after modifying this field it is recommended that the link be fully retrained by setting the FLRET bit in the PHYLSTATE0 register 9...

Страница 117: ...CDE RW 0x0 Sticky Compliance De emphasis This bit selects the de emphasis value in the Polling Compliance state when this state was entered as a result of setting the Enter Compliance ECOMP bit in th...

Страница 118: ...ance with version two of the specification Complies with version the PCI Bus Power Management Interface Specification Revision 1 2 19 PMECLK RO 0x0 PME Clock Does not apply to PCI Express 20 Reserved...

Страница 119: ...essage generation is enabled for the port If a hot plug wake up event is desired when exiting the D3cold state then this bit should be set during serial EEPROM initializa tion A hot reset does not res...

Страница 120: ...te transaction The PES24T3G2 assumes that all downstream port generated MSIs are targeted to the root and routes these transactions to the upstream port Configuring the address contained in a down str...

Страница 121: ...tructure 15 8 NXTPTR RWL 0x00 Next Pointer This field contains a pointer to the next capability structure 31 16 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 15 0...

Страница 122: ...ister SMBus reads of this field return a value of zero and SMBus writes have no effect Bit Field Field Name Type Default Value Description 15 0 CAPID RO 0x1 Capability ID The value of 0x1 indicates an...

Страница 123: ...violation is detected on the port The PES24T3G2 does not support ACS and therefore this bit is hardwired to 0x0 30 22 Reserved RO 0x0 Reserved field 31 DBE RW1C 0x0 Sticky Double Bit Error Status When...

Страница 124: ...ability structure the First Error Pointer field FEPTR in the AERCTL register is not updated and an error is not reported to the root complex This bit does not affect the state of the corresponding bit...

Страница 125: ...lity structure the First Error Pointer field FEPTR in the AERCTL register is not updated and an error is not reported to the root complex This bit does not affect the state of the corresponding bit in...

Страница 126: ...Control Protocol Error Severity If the corresponding event is not masked in the AERUEM register then when the event occurs this bit controls the severity of the reported error If this bit is set the e...

Страница 127: ...event is not masked in the AERUEM register then when the event occurs this bit controls the severity of the reported error If this bit is set the event is reported as a fatal error When this bit is cl...

Страница 128: ...orresponding event is not reported to the root complex 7 BADDLLP RW 0x0 Sticky Bad DLLP Mask When this bit is set the corresponding bit in the AERCES register is masked When a bit is masked in the AER...

Страница 129: ...fault Value Description 4 0 FEPTR RO 0x0 Sticky First Error Pointer This field contains a pointer to the bit in the AERUES register that resulted in the first reported error 5 ECRCGC RWL 0x1 ECRC Gene...

Страница 130: ...ord of the TLP header that resulted in the first reported uncorrectable error Bit Field Field Name Type Default Value Description 15 0 CAPID RO 0x3 Capability ID The value of 0x3 indicates a device se...

Страница 131: ...tion 2 0 EVCCNT RO 0x0 Extended VC Count The value 0x0 indicates only implementa tion of the default VC 3 Reserved RO 0x0 Reserved field 6 4 LPEVCCNT RO 0x0 Low Priority Extended VC Count The value of...

Страница 132: ...e address of the Virtual Channel Capability structure in double quad words 16 bytes The value of zero indicates that the VC arbitration table is not present Bit Field Field Name Type Default Value Des...

Страница 133: ...ted round robin with 128 phases bit 5 weighted round robin with 256 phases 13 8 Reserved RO 0x0 Reserved field 14 APS RO 0x0 Advanced Packet Switching Not supported 15 RJST RO 0x0 Reject Snoop Transac...

Страница 134: ...field 26 24 VCID RO 0x0 VC ID This field assigns a VC ID to the VC resource Since the PES24T3G2 implements only a single VC this field is hardwired to zero 30 27 Reserved RO 0x0 Reserved field 31 VCEN...

Страница 135: ...port arbitration period 15 12 PHASE3 RW 0x4 Phase 3 This field contains the port ID for the corresponding port arbitration period 19 16 PHASE4 RW 0x5 Phase 4 This field contains the port ID for the c...

Страница 136: ...s the port ID for the corresponding port arbitration period 15 12 PHASE19 RW 0x6 Phase 19 This field contains the port ID for the corresponding port arbitration period 19 16 PHASE20 RW 0x7 Phase 20 Th...

Страница 137: ...Capability ID The value of 0x4 indicates a power budgeting capability structure If the power budgeting capability is used then this field should be initialized with data from a serial EEPROM 19 16 CA...

Страница 138: ...wer data for this device should be ignored If the power budgeting capability is used then this field should be initialized with data from a serial EEPROM 31 1 Reserved RO 0x0 Reserved field Bit Field...

Страница 139: ...Upstream port is locked with port 4 0x5 Reserved 27 23 Reserved RO 0x0 Reserved field 31 28 MARKER RW 0x0 Sticky Marker This field is preserved across a hot reset and is available for general softwar...

Страница 140: ...set the Power Budgeting Data Value 7 0 PWRBDV 7 0 registers in all ports may be read and written When this bit is cleared then the PWRBDV registers in all ports are read only 5 DLDHRST RW 0x0 Sticky...

Страница 141: ...i fied device number 0x2 none All TLPs are delivered to the device attached to a link associated with a downstream switch port regardless of the specified device number 0x3 reserved 11 EUIDC RW 0x0 St...

Страница 142: ...y of the PxILOCKP output is inverted in all ports 8 IPXPWRGDN RW 0x0 Sticky Invert Polarity of PxPWRGDN When this bit is set the polarity of the PxPWRGDN input is inverted in all ports 10 9 PDETECT RW...

Страница 143: ...ved 0x3 Reserved 23 16 PWR2RST RW 0x14 Sticky Slot Power to Reset Negation This field contains the delay from stable downstream port power to negation of the down stream port reset in units of 10 mS A...

Страница 144: ...te function or GPIO pin Writing a value to this field causes the corresponding pins which are configured as GPIO outputs to change state to the value written 31 16 Reserved RO 0x0 Reserved field Bit F...

Страница 145: ...k period is equal to 32 ns multiplied by the value in this field When the field is cleared to zero or one the clock is stopped The initial value of this field is 0x0139 when the master SMBus is config...

Страница 146: ...meter is not critical the op erating frequency may be increased Bit Field Field Name Type Default Value Description 15 0 ADDR RW 0x0 EEPROM Address This field contains the byte address in the Serial E...

Страница 147: ...XTM RW 0x0 IO Expander Test Mode Setting this bit puts the I O expander interface into a test mode In this test mode I O expander output signals generated by the PES24T3G2 core are ignored and val ues...

Страница 148: ...I O Expander 3 Address This field contains the SMBus address assigned to I O expander 3 on the master SMBus interface Bit Field Field Name Type Default Value Description 0 Reserved RO 0x0 Reserved fi...

Страница 149: ...s not enabled in the GPECTL register GPEN is an alternate function of GPIO 7 and GPIO 7 is asserted only if enabled to operate as an alternate function 3 Reserved RO 0x0 Reserved field 4 P4GPES RO 0x0...

Страница 150: ...d field 21 19 TLW RW 0x7 Target Link Width This field indicates the target link width when doing dynamic upconfiguration or downconfiguration of the link section Dynamic Link Width Reconfiguration on...

Страница 151: ...The link width was reconfigured but did not reach the target link width 0x3 Failed The link width was not re configured This field may be used by software to determine the success of dynamic upconfigu...

Страница 152: ...UM_WAIT 0xB CFG_LNUM_ACCEPT 0xC CFG_COMPLETE 0xD CFG_IDLE 0xE RESERVE_2 0xF OVR_TMOUT 0x10 REC_RCVR_LOCK 0x11 REC_RCVR_CFG 0x12 REC_IDLE 0x13 REC_SPEED 0x14 L0 0x15 L0s 0x16 L1_ENTRY 0x17 L1_IDLE 0x18...

Страница 153: ...tonomous Link Reliability Management on page 3 6 is enabled 0x0 Autonomous Link Reliability Management Disabled 0x1 Autonomous Link Reliability Management Enabled 1 LET RW 0x0 Sticky Link Error Type T...

Страница 154: ...red by hardware 31 1 Reserved RO 0x0 Reserved field Bit Field Field Name Type Default Value Description 7 0 ERRT RW 0xFF Sticky Error Threshold The value in this field represents the mini mum number o...

Страница 155: ...LRERT register This count remains active when the ALR mechanism is dis abled Please refer to section Autonomous Link Reliability Manage ment on page 3 6 for further details 31 8 MPCNT RO 0x0 Monitorin...

Страница 156: ...IDT Configuration Registers PES24T3G2 User Manual 8 74 February 22 2012 Notes...

Страница 157: ...T3G2 Test Access Point The system logic utilizes a 16 state TAP controller a six bit instruction register and five dedicated pins to perform a variety of functions The primary use of the JTAG TAP Cont...

Страница 158: ...ET active low Asynchronous reset for JTAG TAP controller internal pull up JTAG_TCK Input JTAG Clock Test logic clock JTAG_TMS and JTAG_TDI are sampled on the rising edge JTAG_TDO is output on the fall...

Страница 159: ...3 0 I O PE4RP 3 0 I O PE4TN 3 0 O C PE4TP 3 0 O PEREFCLKN I PEREFCLKP I REFCLKM I O SMBus MSMBADDR 4 1 I O MSMBCLK I O O C MSMBDAT I O O C SSMBADDR 5 3 1 I O SSMBCLK I O O C SSMBDAT I O O C General Pu...

Страница 160: ...passes through the UPDATE IR state whatever value that is currently held in the boundary scan register s output latches is immediately transferred to the corresponding outputs or output enables There...

Страница 161: ...Output Enable Cell is driving a high out to the pad which enables the pad for output and EXTEST is disabled the Capture Cell will be configured to capture output data from the core to the pad However...

Страница 162: ...ontroller passes through the UPDATE DR state these values will be latched onto the output pins or into the output enables Instruction Definition Opcode EXTEST Mandatory instruction allowing the testin...

Страница 163: ...this register to devices further down stream IDCODE The IDCODE instruction is automatically loaded when the TAP controller state machine is reset either by the use of the JTAG_TRST_N signal or by the...

Страница 164: ...tructions Usage Considerations As previously stated there are internal pull ups on JTAG_TRST_N JTAG_TMS and JTAG_TDI However JTAG_TCK also needs to be driven to a known value It is best to either driv...

Страница 165: ...e intended for developers skilled in the art designing with Renesas products You are solely responsible for 1 selecting the appropriate products for your application 2 designing validating and testing...

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