Renesas 89HPES24T3G2ZBAL, Руководство пользователя

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IDT Power Management
PES24T3G2 User Manual 6 - 2 February 22, 2012
Notes
The PES24T3G2 PCI-to-PCI bridges (i.e., ports) have the following behavior when in the D3
hot
power
management state.
– A bridge accepts, processes, and completes all type 0 configuration read and write requests.
– A bridge accepts and processes all message requests that target the bridge.
– All requests received by the bridge on the primary interface, except as noted above, are treated
as unsupported requests (UR).
– Any error message resulting from the receipt of a TLP is reported in the same manner as when
the bridge is not in D3
hot
(e.g, generation of an ERR_NONFATAL message to the root).
– Error messages resulting from any event other than the receipt of a TLP are discarded (i.e., no
error message is generated).
– All completions that target the bridge are treated as unexpected completions (UC).
– Completions flowing in either direction through the bridge are routed as normal. This behavior of
the bridge does not differ from that of the bridge when it is in the D0 power management state.
– All request TLPs received on the secondary interface are treated as unsupported requests (UR).
PME Messages
The PES24T3G2 does not support generation of PME messages from the D3
cold
state. Downstream
ports (i.e., PCI-PCI bridges associated with downstream ports) support the generation of hot-plug PME
events (i.e., a PM_PME power management message) from the D3
hot
state. This includes both the case
when the downstream port is in the D3
hot
state or the entire switch is in the D3
hot
state.
The generation of a PME message by downstream ports necessitates the implementation of a PME
service time-out mechanism to ensure that PME messages are not lost. If the PME Status (PMES) bit in the
a downstream port’s PCI Power Management Control and Status (PMCSR) register is not cleared within the
time-out period specified in the PM_PME Time-Out (PMPMETO) field in the ports PM_PME Timer
(PMPMETIMER) register after a PM_PME message is transmitted, then the PM_PME message is retrans-
mitted and the timer is restarted.
PCI-Express Power Management Fence Protocol
The Root complex takes the following steps to turn off power to a system:
– The root places all devices in the D3 state
– Upon entry to D3, all devices transition their links to the L1 state
– The root broadcasts a PME_Turn_Off message.
– Devices acknowledge the PME_Turn_Off message by returning a PME_TO_ACK message.
From State To State Description
any D0 Uninitialized Power-on Fundamental Reset.
D0 Uninitialized D0 Active PCI-PCI bridge configured by software
D0 Active D3
hot
The Power Management State (PMSTATE) field in the PCI Power Man-
agement Control and Status (PMCSR) register is written with the value
that corresponds to the D3
hot
state.
D3
hot
D0 Uninitialized The Power Management State (PMSTATE) field in the PCI Power Man-
agement Control and Status (PMCSR) register is written with the value
that corresponds to D0 state.
D3
hott
D3
cold
Power is removed from the device.
Table 6.1 PES24T3G2 Power Management State Transition Diagram