NXP Semiconductors MPC5602S, Справочное руководство

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Memory Protection Unit (MPU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 893
24.2.2.5 MPU Region Descriptor Alternate Access Control n (MPU_RGDAACn)
As noted in Section 24.2.2.4.3, MPU Region Descriptor n, Word 2 (MPU_RGDn.Word2) , it is expected
that since system software may adjust only the access controls within a region descriptor
(MPU_RGD
n .Word2) as different tasks execute, an alternate programming view of this 32-bit entity is
desired. If only the access controls are being updated, this operation should be performed by writing to
MPU_RGDAAC
n (Alternate Access Control n ) as stores to these locations do not affect the descriptor’s
valid bit.
The memory address therefore provides an alternate location for updating MPU_RGD n .Word2.
Since the MPU_RGDAAC n register is simply another memory mapping for MPU_RGD n .Word2, the field
definitions shown in Table 24-9 are identical to those presented in Table 24-7 .
Table 24-8. MPU_RGDn.Word3 field descriptions
Field Description
0–7
PID Process Identifier. This 8-bit field specifies that the optional process identifier is to be included in the
determination of whether the current access hits in the region descriptor. This field is combined with the
PIDMASK and included in the region hit determination if MPU_RGDn.Word2[MxPE] is set.
8–15
PIDMASK
Process Identifier Mask. This 8-bit field provides a masking capability so that multiple process identifiers
can be included as part of the region hit determination. If a bit in the PIDMASK is set, then the
corresponding bit of the PID is ignored in the comparison. This field is combined with the PID and
included in the region hit determination if MPU_RGDn.Word2[MxPE] is set. For more information on the
handling of the PID and PIDMASK, see
Section 24.3.1.1, Access evaluation—hit determination .
31
VLD
Valid. This bit signals the region descriptor is valid. Any write to MPU_RGDn.Word{0,1,2} clears this bit,
while a write to MPU_RGDn.Word3 sets or clears this bit depending on bit 31 of the write operand.
0 Region descriptor is invalid
1 Region descriptor is valid
Offset MP 0x800 + (4*n) (MPU_RGDAACn) Access:Read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R M
7
R
E
M
7
W
E
M
6
R
E
M
6
W
E
M
5
R
E
M
5
W
E
M
4
R
E
M
4
W
E
M
3
P
E
M3S
M
M3UM
r w x
M
2
P
E
M2S
M
M2UM
r w x
M
1
P
E
M1S
M
M1UM
r w x
M
0
P
E
M0S
M
M0UM
r w x
W
Reset - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Figure 24-9. MPU RGD Alternate Access Control n (MPU_RGDAACn)
Table 24-9. MPU_RGDAACn field descriptions
Field Description
0
M7RE
Bus master 7 read enable. If set, this flag allows bus master 7 to perform read operations. If cleared, any
attempted read by bus master 7 terminates with an access error and the read is not performed.
1
M7WE
Bus master 7 write enable. If set, this flag allows bus master 7 to perform write operations. If cleared,
any attempted write by bus master 7 terminates with an access error and the write is not performed.
2
M6RE
Bus master 6 read enable. If set, this flag allows bus master 6 to perform read operations. If cleared, any
attempted read by bus master 6 terminates with an access error and the read is not performed.