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Configurable Enhanced Modular IO Subsystem (eMIOS200)

MPC5606S Microcontroller Reference Manual, Rev. 7

264

Freescale Semiconductor

If when entering OPWFMB mode coming out of GPIO mode the internal counter value is not within the
specified range, then the B match will not occur. This will cause the channel internal counter to wrap at
the maximum counter value, which is 0xFFFF for a 16-bit counter. After the counter wrap occurs, it returns
to 0x1 and resumes normal OPWFMB mode operation. Thus in order to avoid the counter wrap condition,
make sure its value is within the 0x1 to B1 register value range when OPWFMB mode is entered.

When a match on comparator A occurs the output register is set to the value of EDPOL. When a match on
comparator B occurs the output register is set to the complement of EDPOL. B1 match also causes the
internal counter to transition to 0x1, thus restarting the counter cycle.

Only values greater than 0x1 are allowed to be written to the B1 register. Loading any other values leads
to unpredictable results.

shows the operation of OPWFMB mode regarding output pin transitions and A1/B1 register

match events. Note that the output pin transition occurs when the A1 or B1 match signal is deasserted,
which is indicated by the A1 match negative edge detection signal. If register A1 is set to 0x4, the output
pin transitions four counter periods after the cycle started, plus one system clock cycle. Note that in the
example shown in

, the internal counter prescaler has a ratio of two.

Figure 9-29. OPWFMB A1 and B1 match to Output Register delay

shows the generated output signal if A1 is set to 0x0. Since the counter does not reach zero in

this mode, the channel internal logic infers a match as if A1 = 0x1, with the difference that in this case, the
positive edge of the match signal is used to trigger the output pin transition instead of the negative edge
used when A1 = 0x1. Note that the A1 positive edge match signal from cycle

n

+ 1 occurs at the same time

as B1 negative edge match signal from cycle

n

. This allows using the A1 positive edge match to mask the

B1 negative edge match when they occur at the same time. The result is that no transition occurs on the
output flip-flop and a 0% duty cycle is generated.

8

1

4

match A1 negative edge detection

5

A1 value

0x000004

A1 match

A1 match negative edge detection

output pin

EDPOL = 0

EMIOSCNT

TIME

match B1 negative edge detection

B1 match

B1 match negative edge detection

B1 value

0x000008

system clock

prescaler

Prescaler ratio = 2

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Содержание MPC5602S

Страница 1: ...MPC5606S Microcontroller Reference Manual Rev 7 Freescale Semiconductor MPC5606S Microcontroller Reference Manual Supports MPC5602S MPC5604S and MPC5606S...

Страница 2: ...rameters including typicals must be validated for each customer application by customer s technical experts Freescale does not convey any license under its patent rights nor the rights of others Frees...

Страница 3: ...1 5 15 Analog to Digital Converter ADC 59 1 5 16 Deserial Serial Peripheral Interface DSPI 60 1 5 17 FlexCAN 61 1 5 18 Serial communication interface module LINFlex 62 1 5 19 System clocks and clock g...

Страница 4: ...Overview 111 4 1 1 2 Features 111 4 1 1 3 Modes of operation 112 4 1 2 External signal description 112 4 1 3 Memory map and register description 112 4 1 3 1 Memory map 113 4 1 3 2 Register description...

Страница 5: ...ngs 135 5 3 3 ADC sampling and conversion timing 135 5 3 4 Programmable analog watchdog 137 5 3 4 1 Introduction 137 5 3 5 DMA functionality 138 5 3 6 Interrupts 138 5 3 7 External decode signals dela...

Страница 6: ...ot Assist Module BAM 6 1 Overview 165 6 2 Features 165 6 3 Boot modes 165 6 4 Memory map 166 6 5 Functional description 166 6 5 1 Entering boot modes 166 6 5 2 Reset Configuration Half Word Source RCH...

Страница 7: ...2 Features 191 8 4 1 3 Modes of operation 192 8 4 2 External signal description 192 8 4 3 Memory map and register definition 192 8 4 3 1 Register descriptions 196 8 4 4 Functional description 204 8 4...

Страница 8: ...tion 224 8 10 2 Main features 224 8 10 3 Block diagram 225 8 10 4 Functional description 225 8 10 4 1 Crystal clock monitor 226 8 10 4 2 PLL clock monitor 226 8 10 4 3 Frequency meter 226 8 10 5 Memor...

Страница 9: ...A Register EMIOSA n 246 9 4 2 6 eMIOS200 UC B Register EMIOSB n 247 9 4 2 7 eMIOS200 UC Counter Register EMIOSCNT n 248 9 4 2 8 eMIOS200 UC Control Register EMIOSC n 248 9 4 2 9 eMIOS200 UC Status Re...

Страница 10: ...288 11 6 External signal description 288 11 6 1 Signal overview 288 11 6 2 Signal names and descriptions 289 11 6 2 1 Peripheral Chip Select Slave Select CS_0 289 11 6 2 2 Peripheral Chip Selects 1 2...

Страница 11: ...SPI transfer format CPHA 0 318 11 8 5 2 Classic SPI transfer format CPHA 1 319 11 8 5 3 Modified SPI transfer format MTFE 1 CPHA 0 320 11 8 5 4 Modified SPI transfer format MTFE 1 CPHA 1 321 11 8 5 5...

Страница 12: ...Control Descriptor L0_4 Register 356 12 3 4 5 Control Descriptor L0_5 Register 358 12 3 4 6 Control Descriptor L0_6 Register 359 12 3 4 7 Control Descriptor L0_7 Register 361 12 3 4 8 Control Descrip...

Страница 13: ...3 4 45 Soft Lock L0_TRANSP Register 401 12 3 4 46 Soft Lock L1_TRANSP Register 402 12 4 Functional description 403 12 4 1 Graphic sources 403 12 4 2 TFT LCD panel configuration 404 12 4 3 DCU mode sel...

Страница 14: ...DI related interrupts 447 12 9 DCU initialization 447 12 10Glossary 448 Chapter 13 DMA Channel Mux DMACHMUX 13 1 Introduction 449 13 1 1 Overview 449 13 1 2 Features 449 13 1 3 Modes of operation 450...

Страница 15: ...er 481 15 3 1 3 DMA Enable Request DMAERQH DMAERQL registers 483 15 3 1 4 DMA Enable Error Interrupt DMAEEIH DMAEEIL registers 484 15 3 1 5 DMA Set Enable Request DMASERQ register 485 15 3 1 6 DMA Cle...

Страница 16: ...rity changing 520 15 5 7 2 Dynamic channel linking and dynamic scatter gather 520 15 5 8 Hardware request release timing 521 Chapter 16 Error Correction Status Module ECSM 16 1 Introduction 523 16 2 O...

Страница 17: ...le Low Mid Address Space Block Locking Register NVLML 561 17 2 6 4 High Address Space Block Locking Register HBL 563 17 2 6 5 Non Volatile High Address Space Block Locking Register NVHBL 563 17 2 6 6...

Страница 18: ...on 600 17 3 6 1 Module Configuration Register MCR 601 17 3 6 2 Low Mid Address Space Block Locking Register LML 605 17 3 6 3 Non Volatile Low Mid Address Space Block Locking Register NVLML 606 17 3 6...

Страница 19: ...nal description 648 17 4 4 1 Access protections 649 17 4 4 2 Read cycles buffer miss 649 17 4 4 3 Read cycles buffer hit 650 17 4 4 4 Write cycles 650 17 4 4 5 Error termination 650 17 4 4 6 Access pi...

Страница 20: ...694 18 3 4 12 Interrupt Flag Register Low IFRL 694 18 3 4 13 Rx Individual Mask Registers RXIMR0 RXIMR63 696 18 4 Functional description 697 18 4 1 Overview 697 18 4 2 Transmit process 698 18 4 3 Arb...

Страница 21: ...JTAG Test Access Port 720 19 8 3 TAP Controller state machine 721 19 8 3 1 Selecting an IEEE 1149 1 2001 register 723 19 8 4 JTAGC instructions 723 19 8 4 1 BYPASS instruction 724 19 8 4 2 ACCESS_AUX...

Страница 22: ...cription 741 20 5 1 General 741 20 5 2 I Bus Protocol 741 20 5 2 1 START Signal 742 20 5 2 2 Slave Address Transmission 743 20 5 2 3 Data Transfer 743 20 5 2 4 Stop Signal 743 20 5 2 5 Repeated START...

Страница 23: ...rces 772 21 6 1 1 Peripheral Interrupt Requests 773 21 6 1 2 Software configurable Interrupt Requests 773 21 6 1 3 Unique Vector for Each Interrupt Request Source 773 21 6 2 Priority management 773 21...

Страница 24: ...on 789 22 4 1 Memory map 789 22 4 2 Register descriptions 790 22 4 2 1 LCD Control Register LCDCR 790 22 4 2 2 LCD Prescaler Control Register LCDPCR 793 22 4 2 3 LCD Contrast Control Register LCDCCR 7...

Страница 25: ...6 LCD waveform examples 821 22 6 1 1 1 Duty multiplexed with 1 1 Bias mode 821 22 6 2 1 2 duty multiplexed with 1 2 Bias mode 822 22 6 3 1 2 duty multiplexed with 1 3 Bias mode 822 22 6 4 1 3 Duty mu...

Страница 26: ...7 2 15 Buffer data register LSB BDRL 857 23 7 2 16 Buffer data register MSB BDRM 857 23 7 2 17 Identifier filter enable register IFER 858 23 7 2 18 Identifier filter match index IFMI 859 23 7 2 19 Id...

Страница 27: ...E 25 1 Introduction 901 25 1 1 Overview 901 25 1 2 Features 903 25 1 3 Modes of operation 903 25 2 External signal description 904 25 3 Memory map and register definition 904 25 3 1 Memory map 905 25...

Страница 28: ...40 25 4 3 3 Peripheral Clocks Disable 941 25 4 3 4 Processor Low Power mode entry 942 25 4 3 5 Processor and system memory clock disable 942 25 4 3 6 Clock sources switch on 942 25 4 3 7 Main Voltage...

Страница 29: ...description 959 26 6 2 1 Nexus Device ID Register DID 959 26 6 2 2 Port Configuration Register PCR 960 26 6 2 3 Development Control Register 1 2 DC1 DC2 962 26 6 2 4 Development Status Register DS 96...

Страница 30: ...ion 979 Chapter 28 Peripheral Bridge PBRIDGE 28 1 Introduction 981 28 1 1 Overview 981 28 1 2 Features 981 28 1 3 Modes of operation 981 28 2 Functional description 981 28 2 1 Access support 981 28 2...

Страница 31: ...dSPI modes of operation 998 30 2 3 1 SPI Master mode 998 30 2 3 2 SPI Slave mode 998 30 2 3 3 Serial Flash mode 998 30 2 3 4 Module Disable mode 998 30 2 3 5 Stop mode 998 30 2 3 6 Debug mode SPI mode...

Страница 32: ...A Control Register QSPI_ACR 1024 30 4 3 19 Serial Flash Mode Status Register QSPI_SFMSR 1025 30 4 3 20 Serial Flash Mode Flag Register QSPI_SFMFR 1027 30 4 3 21 SFM Interrupt and DMA Request Select an...

Страница 33: ...061 30 6 6 2 AHB bus related commands 1061 30 6 6 3 Overview of error flags 1062 30 6 6 4 IP bus and AHB Access command collisions 1062 30 6 7 Command arbitration SFM mode only 1062 30 6 8 DMA usage 1...

Страница 34: ...3 31 4 7 Boot mode capturing 1093 Chapter 32 Real Time Clock RTC API 32 1 Overview 1095 32 2 Features 1095 32 3 Device specific information 1097 32 4 Modes of operation 1097 32 5 Debug support 1098 32...

Страница 35: ...119 35 1 2 3 PWM alignment modes 1120 35 1 2 4 Low power mode 1120 35 1 3 Block diagram 1121 35 2 External signal description 1122 35 2 1 M0C0M M0C0P M0C1M M0C1P PWM output pins for Motor 0 1122 35 2...

Страница 36: ...gn Duty Dither RECIRC Period and PWM mode functions 1139 35 4 2 PWM Duty Cycle 1149 35 4 3 Motor Controller Counter Clock Source 1149 35 4 4 Output switching delay 1150 35 4 5 Operation in SMC stop mo...

Страница 37: ...g Internal States of the SSD 1181 36 6 4 Stepper Motor Transition Considerations 1182 36 6 4 1 SSD Phase In and Phase Out 1182 36 6 4 2 Changing of SSD Internal States 1182 36 6 5 Legacy modes separat...

Страница 38: ...ral 1208 37 6 2 Pad control 1208 37 6 3 General purpose input and output pads GPIO 1208 37 6 4 External interrupts 1209 37 6 4 1 External interrupt management 1210 37 7 Pin muxing 1210 Chapter 38 Syst...

Страница 39: ...1229 40 3 1 Voltage Regulator Control Register VREG_CTL 1229 40 4 Functional description 1230 40 4 1 High Power or Main Regulator HPREG 1230 40 4 2 Low power Regulator LPREG 1230 40 4 3 Ultra Low pow...

Страница 40: ...1 NMI Management 1246 41 5 3 External Wakeups Interrupts 1247 41 5 3 1 External Interrupt Management 1248 41 5 4 On Chip Wakeups 1249 41 5 4 1 On Chip Wakeup Management 1249 Appendix A Registers Under...

Страница 41: ...ystem software and hardware developers and applications programmers who want to develop products with the MPC5606S device It is assumed that the reader understands operating systems microprocessor sys...

Страница 42: ...d or write row indicates that it can be read or written Register field types R Read only Writing this bit has no effect W Write only R W Standard read write bit Only software can change the bit s valu...

Страница 43: ...Developer environment for more information The MPC5606S platform has a single level of memory hierarchy and supports a wide range of on chip SRAM and internal flash memories The 1 MB flash memory vers...

Страница 44: ...dulus counters Two serial communication interface LINFlex modules LINFlex 0 and 1 are master capable LINFlex 0 is also slave capable Two DSPI Deserial Serial Peripheral Interface modules for communica...

Страница 45: ...Stepper Stall Detect SSD Display Control Unit DCU designed to interface with TFT LCD displays Generates all signals required to drive the display and offers blending of four plane data of up to 16 la...

Страница 46: ...vides a summary of the different members of the MPC5606S family This information is intended to provide an understanding of the range of functionality offered by this family Table 1 2 RAM memory scali...

Страница 47: ...locks 32 bit Controller 2 FlexCAN 4 x 4 Peripheral Bridge Peripheral Interrupts from Interrupt Request External Interrupts I O Instructions Data Voltage Regulator NMI SWT STM NMI SIU INTC 4 I2 C 2 LIN...

Страница 48: ...liary FMPLL is available for use as an alternate modulated or non modulated clock source to eMIOS modules and as alternate clock to the DCU for pixel clock generation Crossbar switch architecture enab...

Страница 49: ...tegrated circuit I2 C internal bus controllers with master slave bus interface Up to 133 configurable general purpose pins supporting input and output operations Real Time Counter RTC with multiple cl...

Страница 50: ...ment of the core processor and peripherals Power management features include software controlled clock gating of peripherals and multiple power domains to minimize leakage in low power modes There are...

Страница 51: ...Run modes most processing activity is done One default Drun and four dynamic Run modes are supported Run0 3 The ability to configure and select different Run modes enables different clocks and power c...

Страница 52: ...SoC features Core On CG CG Off Off Peripherals OP OP CG Off2 2 The LCD can optionally be kept running while the device is in Standby mode Off Flash memory OP OP CG Off Off SRAM On On CG CG3 3 All of...

Страница 53: ...of the e200z0 plus Branch acceleration using Branch Target Buffer BTB Supports independent instruction and data accesses to different memory subsystems such as SRAM and flash memory via independent I...

Страница 54: ...al byte reversal of data These instructions can be pipelined to allow effective single cycle throughput Load and store multiple word instructions allow low overhead context save and restore operations...

Страница 55: ...i cycle divide divw and load multiple lmw store multiple smw multiple class instructions can be interrupted to prevent increases in interrupt latency Extensive system development support through Nexus...

Страница 56: ...ed queues and circular queues Source and destination address registers are independently configured to post increment or remain constant Each transfer is initiated by a peripheral CPU periodic timer i...

Страница 57: ...her through software settable interrupt requests These same software settable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority port...

Страница 58: ...be applied to as many as 14 general purpose input pins for noise elimination on external interrupts Register configuration protected against change with soft lock for temporary guard or hard lock to p...

Страница 59: ...5 11 On chip graphics SRAM The MPC5606S microcontroller has 160 KB on chip graphics SRAM with the following features Usable as general purpose SRAM Typical SRAM access time 0 wait state for reads and...

Страница 60: ...annel 16 bit output pulse width modulation input compare output compare As many as five additional channels are configurable as modulus counters eMIOS other features include Selectable clock source fr...

Страница 61: ...e Input Output X X X X X Single Action Input Capture X X X X X Single Action Output Compare X X X X X Modulus Counter Buffered1 1 Modulus up and down counters to support driving local and global count...

Страница 62: ...ith single 32 bit read Independent enabling of function for channels Offset refresh Conversion Triggering support Internal conversion triggering from periodic interrupt timer PIT Four configurable ana...

Страница 63: ...cessing reliable operation in the EMI environment of a vehicle cost effectiveness and required bandwidth The FlexCan modules offer the following Compliant with CAN protocol specification Version 2 0B...

Страница 64: ...imes Programmable baud rate prescalers 13 bit mantissa 4 bit fractional Diagnostic features Loopback Self test LIN bus stuck dominant detection Interrupt driven operation with 16 interrupt sources LIN...

Страница 65: ...lowing features Input frequency range 4 16 MHz Square wave input mode Oscillator input mode 3 3 V 5 0 V Automatic level control PLL reference MPC5606S includes a 32 KHz low power external oscillator f...

Страница 66: ...it up counter with 8 bit prescaler Four 32 bit compare channels Independent interrupt source for each channel Counter can be stopped in debug mode 1 5 23 Software Watchdog Timer SWT The Watchdog featu...

Страница 67: ...whole system data path from the memory to the TFT pads The DCU features the following Display color depth up to 24 bpp Generation of all RGB and control signals for TFT Four layer blending at each pi...

Страница 68: ...ing bit in the LCD RAM Four to six multiplex modes 1 1 1 2 1 3 1 4 1 5 1 6 duty and three bias 1 1 1 2 1 3 methods are available All frontplane and backplane pins can be multiplexed with other port fu...

Страница 69: ...riving small stepper and air core motors used in instrumentation applications This module can be used for other motor control or PWM applications that match the frequency resolution and output drive c...

Страница 70: ...ernally memory mapped resources through JTAG pins Overrun control which selects whether to stall before Nexus overruns or else keep executing and allow overwrite of information Watchpoint triggering w...

Страница 71: ...le Embedded Processors e200z0 Power Architecture Core Reference Manual Variable Length Encoding VLE Programming Environments Manual The aforementioned documents describe all of the functional and elec...

Страница 72: ...the microcontroller input output SIUL module Integration and functional content is provided in the manual as shown in Table 1 6 Table 1 6 Reference manual integration and functional content Chapter In...

Страница 73: ...5606S Microcontroller Data Sheet Certain pins have dedicated functions that affect the behavior of the MCU after reset These include pins to force test or alternate boot conditions and debug features...

Страница 74: ...he modules The ADC functions are enabled using the PCRs 1 8 3 Software design Certain modules provide system integration functions and other modules such as timers provide specific functions From rese...

Страница 75: ...s possible to configure the input output pins and the modules for the application 1 8 4 Other features The MC_ME module manages low power modes and so it is likely that it will be used to switch into...

Страница 76: ...Overview MPC5606S Microcontroller Reference Manual Rev 7 74 Freescale Semiconductor...

Страница 77: ...0x00018000 0x0001FFFF 32 Yes Yes Yes2 Code Flash Array 0 0x00020000 0x0003FFFF 128 Yes Yes Yes2 Code Flash Array 0 0x00040000 0x0005FFFF 128 No Yes Yes2 Code Flash Array 0 0x00060000 0x0007FFFF 128 N...

Страница 78: ...M 0x40000000 0x40001FFF 8 Yes Yes Yes SRAM ECC protection standby support 0x40002000 0x40005FFF 16 Yes Yes Yes SRAM ECC protection in PD2 0x40006000 0x4000BFFF 24 No Yes Yes SRAM ECC protection in PD2...

Страница 79: ...stem Status and Configuration Module SSCM 0xC3FDC000 0xC3FDFFFF 16 Yes Yes Yes Mode Entry Module MC_ME 0xC3FE0000 0xC3FE3FFF 16 Yes Yes Yes Clock Generation Module MC_CGM XOSC IRCOSC FMPLL_0 FMPLL_1 C...

Страница 80: ...800 0xFFE62FFF 2 Yes Yes Yes Stepper Stall Detect SSD3 0xFFE63000 0xFFE637FF 2 Yes Yes Yes Stepper Stall Detect SSD4 0xFFE63800 0xFFE63FFF 2 Yes Yes Yes Stepper Stall Detect SSD5 0xFFE64000 0xFFE6FFFF...

Страница 81: ...A7FFF 64 Reserved 0xFFFA8000 0xFFFABFFF 16 No No Yes QuadSPI 0 0xFFF9C000 0xFFFBFFFF 144 Reserved 0xFFFC0000 0xFFFC3FFF 16 Yes Yes Yes FlexCan 0 CAN0 0xFFFC4000 0xFFFC7FFF 16 No Yes Yes FlexCan 1 CAN1...

Страница 82: ...Memory Map MPC5606S Microcontroller Reference Manual Rev 7 80 Freescale Semiconductor...

Страница 83: ...S Microcontroller Reference Manual Rev 7 Freescale Semiconductor 81 Chapter 3 Signal Description 3 1 Introduction The following sections provide signal descriptions and related information about funct...

Страница 84: ...98 eMIOSA23 SOUND eMIOSA8 FP30 VSSE_A VDDE_A PF9 GPIO 79 SCL_1 PCS0_1 TXD_1 FP31 PF8 GPIO 78 SDA_1 PCS1_1 RXD_1 FP32 PF7 GPIO 77 SCL_0 PCS2_1 FP33 PF6 GPIO 76 SDA_0 FP34 VSS12 VDD12 PF5 GPIO 75 eMIOSA...

Страница 85: ...2 VSS12 VDDA VSSA XTAL32 ANS15 GPIO 45 PC15 EXTAL32 ANS14 GPIO 44 PC14 PCS0_1 MA2 ANS13 GPIO 43 PC13 PCS1_1 MA1 ANS12 GPIO 42 PC12 PCS2_1 MA0 ANS11 GPIO 41 PC11 SOUND ANS10 mux GPIO 40 PC10 ANS9 GPIO...

Страница 86: ...NC G PA10 PA11 PG5 PG6 VSS VSS VSS VSS NC PE7 PE1 NC H PA12 PA13 PA15 PG7 VSS VSS VSS VSS PE5 PE6 VDDMC VSSMC J RESET PA14 PG8 PG10 VSS VSS VSS VSS PE4 PE2 PE0 PD8 K XTAL VDDE_A PG9 PG11 VSS VSS VSS...

Страница 87: ...mpletion Main oscillator pads EXTAL XTAL are tristate Nexus output pads MDO n MCKO EVTO MSEO are forced to output The following pads are pullup PB 6 PH 0 PH 1 PH 3 EVTI 3 4 Voltage supply pins Voltage...

Страница 88: ...between these pins and the nearest VSS12 pin 1 2 V core supply 42 51 103 118 133 50 67 123 148 163 VDDA 3 3 V 5 V ADC supply source 53 69 VDDE_A 3 3 V 5 V I O supply 7 124 7 154 170 VDDE_B 3 3 V 5 V I...

Страница 89: ...tt Trigger characteristics and noise filter I O M Input weak pullup 24 24 J1 XTAL Analog input of the oscillator amplifier circuit Needs to be grounded if oscillator bypass mode is used I X 27 27 K1 E...

Страница 90: ...p P4 MDO3 Nexus message data output 3 M1 O None None 44 A10 MDO3 Nexus message data output 3 M1 O Input Pullup L4 MSEO Nexus message start end output M1 O None None 34 C12 MSEO Nexus message start end...

Страница 91: ...PA 2 PCR 2 Option 0 Option 1 Option 2 Option 3 GPIO 2 DCU_R2 eMIOSA 20 FP21 SIUL DCU PWM Timer I O M1 None None 137 167 C1 PA 3 PCR 3 Option 0 Option 1 Option 2 Option 3 GPIO 3 DCU_R3 eMIOSA 19 FP20 S...

Страница 92: ..._G3 eMIOSA 13 FP12 SIUL DCU PWM Timer I O M1 None None 2 2 G2 PA 12 PCR 12 Option 0 Option 1 Option 2 Option 3 GPIO 12 DCU_G4 eMIOSA 12 FP11 SIUL DCU PWM Timer I O M1 None None 3 3 H1 PA 13 PCR 13 Opt...

Страница 93: ...I O S None None 111 139 R13 PB 4 PCR 20 Option 0 Option 1 Option 2 Option 3 GPIO 20 SCK_1 MA0 SIUL DSPI_1 ADC I O M1 None None 48 62 P8 PB 5 PCR 21 Option 0 Option 1 Option 2 Option 3 GPIO 21 SOUT_1 M...

Страница 94: ...Option 2 Option 3 GPIO 27 CANTX_1 PDI3 eMIOSA 16 SIUL FlexCAN_1 PDI PWM Timer I O M1 None None 108 132 N12 PB 12 PCR 28 Option 0 Option 1 Option 2 Option 3 GPIO 28 RXD_1 eMIOSB 19 PCS2_0 SIUL LINFlex_...

Страница 95: ...3 GPIO 34 ANS 4 SIUL I O J None None 68 84 R11 PC 5 PCR 35 Option 0 Option 1 Option 2 Option 3 GPIO 35 ANS 5 SIUL I O J None None 67 83 P11 PC 6 PCR 36 Option 0 Option 1 Option 2 Option 3 GPIO 36 ANS...

Страница 96: ...ADC DSPI_1 I O J None None 58 74 P9 PC 13 PCR 43 Option 0 Option 1 Option 2 Option 3 GPIO 43 MA2 PCS0_1 ANS 13 SIUL ADC DSPI_1 I O J None None 57 73 N9 PC 14 PCR 44 Option 0 Option 1 Option 2 Option...

Страница 97: ...SB 19 SIUL SMC SSD PWM Timer I O SMD None None 79 95 N15 PD 5 PCR 51 Option 0 Option 1 Option 2 Option 3 GPIO 51 M1C0P SSD1_1 eMIOSB 18 SIUL SMC SSD PWM Timer I O SMD None None 80 96 M15 PD 6 PCR 52 O...

Страница 98: ...SMC SSD I O SMD None None 89 105 L14 PD 13 PCR 59 Option 0 Option 1 Option 2 Option 3 GPIO 59 M3C0P SSD3_1 SIUL SMC SSD I O SMD None None 90 106 K14 PD 14 PCR 60 Option 0 Option 1 Option 2 Option 3 GP...

Страница 99: ...GPIO 66 M5C0M SSD5_0 eMIOSA 11 SIUL SMC SSD PWM Timer I O SMD None None 99 115 J13 PE 5 PCR 67 Option 0 Option 1 Option 2 Option 3 GPIO 67 M5C0P SSD5_1 eMIOSA 10 SIUL SMC SSD PWM Timer I O SMD None No...

Страница 100: ...MI I O S None None 37 45 L3 PF 3 PCR 73 Option 0 Option 1 Option 2 Option 3 GPIO 73 eMIOSA 11 PDI6 FP37 SIUL PWM Timer PDI I O M1 None None 115 145 C8 PF 4 PCR 74 Option 0 Option 1 Option 2 Option 3 G...

Страница 101: ...QuadSPI I O M1 None None 127 157 A14 PF 11 PCR 81 Option 0 Option 1 Option 2 Option 3 GPIO 81 eMIOSB 23 IO2 PCS1_26 FP28 SIUL PWM Timer QuadSPI I O M1 None None 128 158 A15 PF 12 PCR 82 Option 0 Opti...

Страница 102: ...P5 SIUL DCU PWM Timer I O M2 None None 11 11 E4 PG 3 PCR 89 Option 0 Option 1 Option 2 Option 3 GPIO 89 DCU_B3 eMIOSB 21 FP4 SIUL DCU PWM Timer I O M1 None None 12 12 F3 PG 4 PCR 90 Option 0 Option 1...

Страница 103: ...on 3 GPIO 96 DCU_DE BP2 SIUL DCU I O M2 None None 19 19 J4 PG 11 PCR 97 Option 0 Option 1 Option 2 Option 3 GPIO 97 DCU_PCLK BP3 SIUL DCU I O M1 None None 20 20 K4 PG 12 PCR 98 Option 0 Option 1 Optio...

Страница 104: ...t Pullup 35 41 M3 PH 4 PCR 103 Option 0 Option 1 Option 2 Option 3 GPIO 103 PCS0_0 eMIOSB 16 CLKOUT SIUL DSPI_0 PWM Timer Control I O F None None 47 61 R5 PH 5 PCR 104 Option 0 Option 1 Option 2 Optio...

Страница 105: ...122 A4 PJ 4 PCR 109 Option 0 Option 1 Option 2 Option 3 GPIO 109 PDI 0 CANRX_0 SIUL PDI FlexCAN_0 I O S None None 57 B4 PJ 5 PCR 110 Option 0 Option 1 Option 2 Option 3 GPIO 110 PDI 1 CANTX_0 SIUL PDI...

Страница 106: ...D5 PJ 12 PCR 117 Option 0 Option 1 Option 2 Option 3 GPIO 117 PDI 8 eMIOSB 17 SIUL PDI PWM Timer I O M1 None None 135 C6 PJ 13 PCR 118 Option 0 Option 1 Option 2 Option 3 GPIO 118 PDI 9 eMIOSB 20 SIU...

Страница 107: ...3 GPIO 124 MSEO PDI 11 SIUL Nexus PDI I O M1 None None 34 C12 PK 4 PCR 125 Option 0 Option 1 Option 2 Option 3 GPIO 125 EVTO PDI 12 SIUL Nexus PDI I O M1 None None 35 D12 PK 5 PCR 126 Option 0 Option...

Страница 108: ...function is reported as 2 Special functions are enabled independently from the standard digital pin functions Enabling standard I O functions in the PCR registers may interfere with their functionali...

Страница 109: ...AM Alternate Boot Select Gives an option to boot by downloading code via CAN or LIN ANS 0 15 ADC Inputs used to bring into the device sensor based signals for A D conversion ANS 0 15 connect to ATD ch...

Страница 110: ...6 23 eMIOS Enhanced Modular Input Output System 16 8 channel eMIOS for timed input or output functions CANRX_0 CANRX_1 FlexCAN Receive RX pins for the CAN bus transceiver CANTX_0 CANTX_1 FlexCAN Trans...

Страница 111: ..._PCLK DCU PDI Input pixel clock from PDI PDI_VSYNC DCU PDI Input indicates the timing reference for the start of a frame for the PDI input data RXD_0 LINFlex SCI LIN Receive data signal This port is u...

Страница 112: ...Signal Description MPC5606S Microcontroller Reference Manual Rev 7 110 Freescale Semiconductor...

Страница 113: ...n module is located between the module under protection and the PBRIDGE This is shown in Figure 4 1 Figure 4 1 Register Protection block diagram 4 1 1 2 Features The Register Protection includes these...

Страница 114: ...1 is 6 KB starting at address 0x0000 and holds the normal functional module registers and is transparent for all read write operations Area 2 is 2 KB starting at address 0x1800 and is a reserved area...

Страница 115: ...rue even if not all accessed bytes are locked Accessing unimplemented 32 bit registers in Areas 4 and 5 will result in a transfer error 4 1 3 1 Memory map Table 4 1 gives an overview of the Register P...

Страница 116: ...nism Each MR is protectable by one associated bit in a SLBRn SLBm according to the mapping described in Table 4 2 4 1 3 2 3 Soft Lock Bit Register SLBR0 1535 These registers hold the Soft Lock Bits fo...

Страница 117: ...20 21 22 23 24 25 26 27 28 29 30 31 R H L B 0 0 0 0 0 0 0 U A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 4 4 Global...

Страница 118: ...to be changed This can be done using the following methods Modify the SLBRn SLBm directly by writing to area 4 Set the SLBRn SLBm bit s by writing to the mirror module space area 3 Both methods are ex...

Страница 119: ...main unchanged In the example on the left side of Figure 4 6 the data written to SLBRn SLB 0 is mirrored to SLBRn SLB 1 and the data written to SLBRn SLB 2 is mirrored to SLBRn SLB 3 as for both regis...

Страница 120: ...ed module are updated The corresponding lock bits remain unchanged left part of Figure 4 6 When writing to address 0x2008 the registers MR9 and MR8 in the protected module are updated The correspondin...

Страница 121: ...access error from the underlying Module under Protection 2 If user mode is not allowed user writes to all areas will assert a transfer error and the writes will be blocked 3 If accessing the reserved...

Страница 122: ...mode or regular servicing Programmable selection of reset or interrupt on an initial timeout Master access protection Hard and soft configuration lock bits The SWT is started on Phase1 exit and counts...

Страница 123: ...s Otherwise a bus error is generated If either the HLK or SLK bits in the SWT_CR are set then the SWT_CR SWT_TO and SWT_WN registers are read only Table 4 5 SWT operation after reset SWT_CR WEN MCU mo...

Страница 124: ...only Reset Value Location 0x0000 SWT Control Register SWT_CR R W 0xFF00_011B on page 122 0x0004 SWT Interrupt Register SWT_IR R W 0x0000_0000 on page 123 0x0008 SWT Timeout Register SWT_TO R W 0x0003_...

Страница 125: ...the value in the SWT_WN register ITR Interrupt Then Reset 0 Generate a reset on a timeout 1 Generate an interrupt on an initial timeout reset on a second consecutive timeout HLK Hard Lock This bit is...

Страница 126: ...0 0 0 0 0 0 0 0 0 0 0 0 Figure 4 13 SWT Interrupt Register SWT_IR Table 4 8 SWT_IR field descriptions Field Description TIF Timeout Interrupt Flag The flag and interrupt are cleared by writing a 1 to...

Страница 127: ...ow Register SWT_WN Table 4 10 SWT_WN Register field descriptions Field Description WST Window start value When window mode is enabled the service sequence can only be written when the internal down co...

Страница 128: ...CNT Watchdog Count When the watchdog is disabled SWT_CR WEN 0 this field shows the value of the internal down counter When the watchdog is enabled the value of this field is 0x0000_0000 Values in thi...

Страница 129: ...either case when locked the SWT_CR SWT_TO and SWT_WN registers are read only The hard lock is enabled by setting the SWT_CR HLK bit which can only be cleared by a reset The soft lock is enabled by set...

Страница 130: ...load the down counter with the timeout period If the service sequence is not written before the second consecutive timeout the SWT generates a system reset The interrupt is indicated by the timeout in...

Страница 131: ...3 data registers for storing converted data conversion information such as mode of operation normal injected is associated to data value Conversions on external channels managed in the same way as int...

Страница 132: ...d standard accuracy channels External ANX externally multiplexed standard accuracy channels The mask registers present within the ADCDig can be programmed to configure which channel is to be converted...

Страница 133: ...R the normal conversion can be started in two ways By software TRGEN reset If the external trigger enable bit is reset the conversion chain starts when the NSTART bit in the MCR is set By trigger TRGE...

Страница 134: ...ersion phase when the sampled analog value is converted to digital as shown in Figure 5 2 Figure 5 2 Normal conversion flow In One Shot mode MODE 0 a sequential conversion specified in the NCMR regist...

Страница 135: ...it in the MSR Example 5 2 Scan mode MODE 1 Channels A B C D E F G H are present in the device where channels B D E are to be converted in Scan mode MODE 1 is set for Scan mode Conversion starts from c...

Страница 136: ...provided The user can abort the ongoing conversion by setting the ABORT bit in the MCR The current conversion is aborted and the conversion of the next channel of the chain is immediately started gen...

Страница 137: ...the conversion still requires a 16 MHz clock an 8 MHz clock is not fast enough In all other cases the ADC should use the clock divided by two internally 5 3 3 ADC sampling and conversion timing In or...

Страница 138: ...elated configuration settings INPLATCH INPCMP INPSAMP AD_clk fmax MHz Tsample min ns 0 0x1 0x3 20 125 0 0x1 0x4 20 4 168 1 0x2 0x4 20 4 168 1 0x2 0x5 20 4 135 1 0x3 0x7 32 4 132 1 0x3 0x7 40 4 128 1 0...

Страница 139: ...n Table 5 4 Depending on the mask bits MSKWDGxL and MSKWDGxH in the WTIMR an interrupt is generated on threshold violation The channel on which the analog watchdog is to be applied is selected by the...

Страница 140: ...that situation as it could lead to misinterpretation of the watchdog interrupts 5 3 5 DMA functionality A DMA request can be programmed after the conversion of every channel by setting the respective...

Страница 141: ...e field DSD 0 7 When this programmed delay is taking place the ADCSTATUS 0 2 field in the Main Status Register MSR will display the value 010 wait state 5 3 8 Power down mode The analog part of the AD...

Страница 142: ...Mask Register CIMR1 028 0x0000_0000 Channel Interrupt Mask Register CIMR2 02C 0x0000_0000 Watchdog Threshold Interrupt Status Register WTISR 030 0x0000_0000 Watchdog Threshold Interrupt Mask Register...

Страница 143: ...000_0000 Channel 36 Data Register CDR36 190 0x0000_0000 Channel 37 Data Register CDR37 194 0x0000_0000 Channel 38 Data Register CDR38 198 0x0000_0000 Channel 39 Data Register CDR39 19C 0x0000_0000 Cha...

Страница 144: ...1 When any of the extended channels is used ch42 is irrelevant because the single pin PC 10 shares the functionality of either dedicated ch42 or all 8 extended channels of analog input coming from the...

Страница 145: ...e This bit enables or disables the functionality to overwrite unread converted data 0 Prevents overwrite of unread converted data new result is discarded 1 Enables converted data to be overwritten by...

Страница 146: ...channel injection 10 JEDGE Injection trigger edge selection Edge selection for external trigger if JTRGEN 1 0 Selects falling edge for the external trigger 1 Selects rising edge for the external trigg...

Страница 147: ...ed 0 Conversion is not affected 1 Aborts the ongoing conversion Note If the abort pulse is valid in the last cycle of the SAMPLE phase the current channel is correctly aborted but the data register CD...

Страница 148: ...ys high while the conversion is ongoing or pending during injection mode 8 JABORT This status bit signals that an injected conversion has been aborted This bit is reset when a new injected conversion...

Страница 149: ...0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 JEOC JECH EOC ECH W w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 7 Interrupt Status Register ISR Tab...

Страница 150: ...l end of conversion When this bit is set an EOC interrupt has occurred 31 ECH End of Chain Conversion interrupt ECH flag It is the interrupt of the digital end of chain conversion When this bit is set...

Страница 151: ...C_CH78 EOC_CH77 EOC_CH76 EOC_CH75 EOC_CH74 EOC_CH73 EOC_CH72 EOC_CH71 EOC_CH70 EOC_CH69 EOC_CH68 EOC_CH67 EOC_CH66 EOC_CH65 EOC_CH64 W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c R...

Страница 152: ...27 Reserved Must be kept at 0 28 MSKJEOC Mask bit for JEOC When set the JEOC interrupt is enabled 29 MSKJECH Mask bit for JECH When set the JECH interrupt is enabled 30 MSKEOC Mask bit for EOC When se...

Страница 153: ...M 69 CIM 68 CIM 67 CIM 66 CIM 65 CIM 64 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 12 Channel Interrupt Mask Register 2 CIMR2 Table 5 12 CIMRn field descriptions Field Description CIMn This fiel...

Страница 154: ...o the programmed lower threshold no interrupt generated 1 Converted value is lower than the programmed lower threshold interrupt is generated Address Base 0x0034 Access User read write 0 1 2 3 4 5 6 7...

Страница 155: ...0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCL R DMA EN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 15 DMA Enable Register DMAE Table 5 15 DMA Enable Registe...

Страница 156: ...19 20 21 22 23 24 25 26 27 28 29 30 31 R DMA 47 DMA 46 DMA 43 DMA 44 DMA 43 DMA 42 DMA 41 DMA 40 DMA 39 DMA 38 DMA 37 DMA 36 DMA 35 DMA 34 DMA 33 DMA 32 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure...

Страница 157: ...19 20 21 22 23 24 25 26 27 28 29 30 31 THR EN THR INV Res Reserved THRCH rw rw rw Figure 5 18 Threshold Control Register TRCx x 0 3 Table 5 17 Threshold Control Register TRCx x 0 3 field descriptions...

Страница 158: ...4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 THRH W Reset 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 THRL W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figu...

Страница 159: ...isters CTR 1 2 Table 5 19 Conversion timing registers CTR 1 2 field descriptions Field Description 0 15 Reserved A write of any value has no effect The read value is always 0 16 INPLATCH Configuration...

Страница 160: ...e bits of normal sampling for channel 32 to 63 extended internal channels Reset value 0x0000_0000 Address Base 0x00A8 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CH63 CH62 CH61 CH60...

Страница 161: ...H48 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CH47 CH46 CH45 CH44 CH43 CH42 CH41 CH40 CH39 CH38 CH37 CH36 CH35 CH34 CH33 CH32 W Reset 0 0 0 0 0 0 0 0 0...

Страница 162: ...Figure 5 24 Decode Signals Delay Register DSDR Table 5 22 Decode Signals Delay Register DSDR field descriptions Field Description 0 23 Reserved A write of any value has no effect The read value is al...

Страница 163: ...18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 PDED 0 7 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 25 Power down Exit Delay Register PDEDR Table 5 23 Power down Exit Delay Register...

Страница 164: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 CDATA 0 9 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 5 26 Channel Data Register CDR 0 95 Table 5 24 Ch...

Страница 165: ...ion for the corresponding channel 00 Data is a result of normal conversion mode 01 Data is a result of injected conversion mode 10 Reserved 11 Reserved 16 21 Reserved A write of any value has no effec...

Страница 166: ...Analog to Digital Converter ADC MPC5606S Microcontroller Reference Manual Rev 7 164 Freescale Semiconductor...

Страница 167: ...application boot code MPC5606S in static mode if internal flash is not initialized or invalid System can recover from Static mode only by Reset Programmable 64 bit password protection for serial boot...

Страница 168: ...ernal pins and device status see Figure 6 1 To boot either from FlexCAN or LINFlex the device must be forced into an Alternate Boot Loader mode via the FAB Force Alternate Boot mode pin which must be...

Страница 169: ...AB ABS Standby RAM boot flag Boot ID Boot mode 1 0 0 LINFlex 1 1 0 FlexCAN 0 0 valid SC Single chip 0 0 not found Static mode POR FABM 1 ABS Serial Boot SBL LINFlex Serial Boot SBL FlexCAN Y ABS 0 ABS...

Страница 170: ...rs shown in Table 6 4 Each boot sector contains at offset 0x00 the Reset Configuration Half Word RCHW 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Reserved BOOT_ID 0 7 W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Страница 171: ...n this sector and reads the 32 bit word at offset 0x4 This word is the address where the startup code is located reset boot vector Table 6 4 Flash boot sector Block Address 0 0x0000_0000 1 0x0000_8000...

Страница 172: ...est is the alternate boot sector The alternate boot sector does not need to be consecutive to the main boot sector This scheme ensures that there is always one active boot sector by erasing one of the...

Страница 173: ...ster see Section 38 2 2 1 System Status Register STATUS indicate which boot has to be executed see Table 6 5 If BMODE field shows either a single chip value 011 or the reserved values the boot mode is...

Страница 174: ...ck the boot mode and during password check see Table 6 5 and Figure 6 5 External oscillator SWT the BAM disables it The following hardware resources are used only when autobaud feature is selected STM...

Страница 175: ...n continue to send data If data is not correct the host stops transmitting and the MCU needs to be reset All multi byte data structures are sent with MSB first A more detailed description of these ste...

Страница 176: ...nd BAM continues its task SEC 1 flash is still secured because password was wrong BAM puts MCU into static mode This fixed time depends on the external crystal oscillator frequency FXOSC With FXOSC of...

Страница 177: ...ments until the number of bytes of data received matches the number of bytes specified in the previous protocol step Since the SRAM is protected by a 32 bit wide Error Correction Code ECC BAM always w...

Страница 178: ...ocol and BAM action during this boot mode Table 6 7 UART Boot mode download protocol autobaud disabled Protocol step Host sent message BAM response message Action 1 64 bit password MSB first 64 bit pa...

Страница 179: ...lator The FlexCAN controller is configured to operate at a baud rate system clock frequency 40 see Table 6 6 for examples of baud rate It uses the standard 11 bit identifier format detailed in FlexCAN...

Страница 180: ...dress is stored for future use Size of download is stored for future use Verify if VLE bit is set to 1 3 CAN ID 0x013 8 to 64 bits of raw binary data CAN ID 0x003 8 to 64 bits of raw binary data 8 bit...

Страница 181: ...1 To download the code via serial boot the provided password is 0x1234_5678_8765_4321 NVPWD1 followed by NVPWD0 When the flash memory is unsecured the registers are programmed as follows NVPWD0 0x8765...

Страница 182: ...Boot Assist Module BAM MPC5606S Microcontroller Reference Manual Rev 7 180 Freescale Semiconductor...

Страница 183: ...which low power mode is used it is possible to catch either the first or the second CAN frame by sampling one of two CAN Rx ports and storing all samples in internal registers After selection of the...

Страница 184: ...ption The CAN registers are listed in Table 7 1 7 3 1 CAN Sampler Control Register Table 7 1 CAN registers Register Name Address Offset Reset Value Location Control Register CR 00h 0000 0000h on page...

Страница 185: ...23 25 CAN_RX_SEL These bits determine which RX bit is sampled 000 Rx0 is selected 001 Rx1 is selected 010 Rx2 is selected 011 Rx3 is selected 100 Rx4 is selected 101 Rx5 is selected not valid on this...

Страница 186: ...software must enable the sampler by setting the CAN_SMPLR_EN bit in the CR register It then becomes the master controller for accessing the internal registers implemented for storing samples When ena...

Страница 187: ...d by the kernel of the sampler You can monitor CR Active_CK to check which is the active clock to the registers If there is any activity on the selected Rx line the sampler enables the 16 MHz RC oscil...

Страница 188: ...efore going into Standby or Stop mode This is done by setting BRP bits 5 1 in the Control register The reset value of BRP is 00000 and can be set to a maximum of 11111 which gives a prescale value of...

Страница 189: ...m three sources External oscillator FXOSC 4 16 MHz High speed internal RC 16 MHz FMPLL0 clocked by FXOSC still one of system clock sources Additionally there are two low power oscillators Low speed in...

Страница 190: ...2 4 8 PLL0_Clk eg 64 MHz FIRC_clk FXOSC_clk CLKOUT Selector Peripheral 1 to 32 1 to 32 FIRC_clk_divided FXOSC_clk_divided eMIOS_1 8ch eMIOS_0 16ch 1 to 16 1 to 16 Note no clock monitor associated wit...

Страница 191: ...r Configuration Registers CGM_SC_DC0 2 In the case of the DCU eMIOS_0 eMIOS_1 and QuadSPI peripherals there is a choice of source clocks For the eMIOS0 and eMIOS1 peripherals there is the option to fu...

Страница 192: ...em clock The MC_ME controls the system clock selection see the MC_ME chapter for more details Peripheral clock selection is controlled by MC_CGM control registers A set of MC_CGM registers controls th...

Страница 193: ...ng to MC_ME control Contains a set of registers to control clock dividers for divided clock generation Contains a set of registers to control peripheral clock selection Supports multiple clock sources...

Страница 194: ...ster content Cause a transfer error Table 8 2 MC_CGM register description Address Name Description Size Access 0xC3FE_0370 CGM_OC_EN Output Clock Enable word read write 0xC3FE_0374 CGM_OCDS_SC Output...

Страница 195: ...xC3FE_0020 0xC3FE_003C Reserved 0xC3FE_0040 0xC3FE_005C SXOSC registers 0xC3FE_0060 0xC3FE_007C FIRC registers 0xC3FE_0080 0xC3FE_009C Reserved 0xC3FE_00A0 0xC3FE_00BC FMPLL0 registers 0xC3FE_00C0 0xC...

Страница 196: ...5C Reserved 0xC3FE_0260 0xC3FD_C27C Reserved 0xC3FE_0280 0xC3FE_029C Reserved 0xC3FE_02A0 0xC3FE_02BC Reserved 0xC3FE_02C0 0xC3FE_02DC Reserved 0xC3FE_02E0 0xC3FE_02FC Reserved 0xC3FE_0300 0xC3FE_031C...

Страница 197: ...0 0 0 0 0 0 0 0 0 0 W 0xC3FE_037C CGM_SC_DC0 2 R DE0 0 0 0 DIV0 DE1 0 0 0 DIV1 W R DE2 0 0 0 DIV2 0 0 0 0 0 0 0 0 W 0xC3FE_0380 CGM_AC0_SC R 0 0 0 0 SELCTL 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 0 0 0 0 0 0 0...

Страница 198: ...R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0xC3FE_0394 CGM_AC2_DC0 R DE0 0 0 0 DIV0 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W 0xC3FE_0398 CGM_AC3_SC R 0 0 0 0 SELCTL 0 0 0 0 0 0 0 0 W R 0 0 0 0 0...

Страница 199: ...0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8 4 Output Clock Division Select Register CGM_OCD...

Страница 200: ...tus Register CGM_SC_SS field descriptions Field Description SELSTAT System Clock Source Selection Status This value indicates the clock source for the system clock 0000 16 MHz internal RC oscillator 0...

Страница 201: ...e system clock divider 1 1 Enable system clock divider 1 DIV1 Divider 1 Division Value The resultant peripheral set 2 clock will have a period DIV1 1 times that of the system clock If the DE1 is set t...

Страница 202: ...0000 4 16 MHz external oscillator 0001 16 MHz internal RC oscillator 0010 Secondary FMPLL 0011 Primary FMPLL 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 re...

Страница 203: ...101 reserved 1110 reserved 1111 reserved Address 0xC3FE_038C Access Supervisor read write User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DE0 0 0 0 DIV0 0 0 0 0 0 0 0 0 W Reset 1 0 0 0 0 0 0 0...

Страница 204: ...SC Table 8 11 Auxiliary Clock 2 Select Control Register CGM_AC2_SC field descriptions Field Description SELCTL Auxiliary Clock 2 Source Selection Control This value selects the current source for auxi...

Страница 205: ...ield is ignored and the eMIOS1 clock remains disabled Address 0xC3FE_0398 Access Supervisor read write User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 SELCTL 0 0 0 0 0 0 0 0 W Reset 0 0...

Страница 206: ...normal operation the system clock selection is controlled by MC_RGM on a Safe mode event MC_ME in all other cases 8 4 4 1 2 System clock disable During normal operation the system clock can be disabl...

Страница 207: ...er 1 0 MC_ME clock select MC_RGM safe clock request MC_ME system clock switch mask CGM_SC_DC0 Register clock divider CGM_SC_DC2 Register clock divider CGM_SC_DC1 Register clock divider peripheral set...

Страница 208: ...Figure 8 15 MC_CGM Auxiliary Clock 1 Generation Overview CGM_AC0_SC Register DCU clock 0 16 MHz internal RC oscillator 1 3 2 Primary FMPLL Secondary FMPLL 4 16 MHz external oscillator CGM_AC1_SC Regis...

Страница 209: ...normal operation the auxiliary clock selection is done via the CGM_AC0 3_SC registers If software selects an unavailable source the old selection remains and the register content does not change CGM_A...

Страница 210: ...clock multiplexing The MC_CGM contains a multiplexing function for a number of clock sources which can then be used as output clock sources The selection is done via the CGM_OCDS_SC register Figure 8...

Страница 211: ...tatus After system reset the oscillator is powered down and software has to restart it when required Whenever the crystal oscillator is switched on from the off state the OSCCNT counter starts When it...

Страница 212: ...reset this bit 0 Oscillator output is used as root clock 1 EXTAL is used as root clock 8 15 EOCV 7 0 End of Count Value These bits specify the end of count value to be used for comparison by the oscil...

Страница 213: ...wer down state and software has to start it up when required Whenever the crystal oscillator is switched on from an off state the OSCCNT counter starts When it reaches the value of EOCV 7 0 512 the os...

Страница 214: ...t System reset is needed to reset this bit 0 Oscillator output is used as root clock 1 EXTAL32 is used as root clock 8 15 EOCV 7 0 End of Count Value These bits specify the end of count value to be us...

Страница 215: ...r divided by a configurable division factor in the range 1 to 32 to generate the divided clock to match system requirements This division factor is specified by the LPRCDIV 4 0 bits of the LPRC_CTL re...

Страница 216: ...urable division factor in the range 1 to 32 to generate the divided clock to match system requirements This division factor is specified by the RCDIV 4 0 bits of the RC_CTL register Base Address 0xC3F...

Страница 217: ...writable only in supervisor mode 8 9 Frequency modulated phase locked loops and system clocks FMPLL0 and FMPLL1 8 9 1 Introduction This section describes the features and functions of the two independ...

Страница 218: ...3 Features Each FMPLL has the following major features Input clock frequency from 4 MHz to 16 MHz Voltage controlled oscillator VCO range from 256 MHz to 512 MHz Reduced frequency divider RFD for redu...

Страница 219: ...l Register CR Table 8 20 FMPLL Memory map Address Register Access Location Base 0xC3FE00A0 FMPLL0 0xC3FE00C0 FMPLL1 0x0000 Control Register CR R W on page 217 0x0004 Modulation Register MR Special on...

Страница 220: ...munications until the division has finished 24 mode This bit activates the 1 1 mode 25 unlock_once This bit is a sticky indication of PLL loss of lock condition The unlock_once bit is set when the PLL...

Страница 221: ...15 1111 Clock Inhibit Table 8 23 Output divide ratios ODF 1 0 Output divide ratios 00 Divide by 2 01 Divide by 4 10 Divide by 8 11 Divide by 16 Table 8 24 Loop divide ratios NDIV 6 0 loop divide ratio...

Страница 222: ...to bypass the STRB signal used inside PLL to latch the correct values for control bits INC_STEP MOD_PERIOD and SPRD_SEL 0 STRB is used to latch PLL modulation control bits 1 STRB is bypassed In this c...

Страница 223: ..._pll_sw bit in CR Then when the input pin pll_select goes high the output clock ck_pll_div will progressively increase its frequency as described in Table 8 26 and Figure 8 26 16 FM_EN Frequency Modul...

Страница 224: ...de the PLL two ways are used depending on the value of the STRB_BYPASS register bit in MR If STRB_BYPASS is low the modulation parameters are latched in the PLL only when the STRB signal goes high for...

Страница 225: ...ameters have no influence on the output clock In fact the dividers and the FM control are bypassed inside the PLL The PLL output clock phi frequency is determined by the following relation 8 9 7 Recom...

Страница 226: ...illator clock the speed of which must be greater than the internal RC clock divided by a division factor given by the RCDIV 1 0 field of the CMU_CSR register and when enabled generates a system clock...

Страница 227: ...CK_FIRC clock from the high frequency internal RC oscillator CK_PLL clock from the PLL FOSC frequency of external crystal oscillator clock FRCslow frequency of low frequency internal RC oscillator FRC...

Страница 228: ...then the event pending bit FLCI in CMU_ISR will be set If FPLL is less than a reference value determined by the LFREF 11 0 bits of CMU_LFREFR and the CK_PLL is ON as signaled by the MC_ME then An even...

Страница 229: ...erface Register Set Base address 0xC3FE_0100 Register Name Address Offset Location Control Status Register CMU_CSR 0x00 on page 228 Frequency Display Register CMU_FDR 0x04 on page 229 High Frequency R...

Страница 230: ...y hardware when the measure is ready in the CMU_FDR register 0 Frequency measurement is completed or not yet started 1 Frequency measurement is not completed 22 23 CKSEL1 RC Oscillator s selection bit...

Страница 231: ...12 31 FD Measured frequency bits This register displays the measured frequency FRC with respect to FOSC The measured value is given by the following formula FRC FOSC MD n where n is the value in the C...

Страница 232: ...ference value These bits determine the low reference value for the FMPLL0 The reference value is given by LFREF 11 0 16 FRCfast 4 Offset 0x0010 Access Read Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15...

Страница 233: ...by the MC_ME It can be cleared by software by writing 1 0 No OLR event 1 OLR event is pending Address offset 0x18 Access Read Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 MD...

Страница 234: ...Clock Description MPC5606S Microcontroller Reference Manual Rev 7 232 Freescale Semiconductor...

Страница 235: ..._1 is an 8 channel module 9 1 1 Unsupported features Real time signal bus client Wheel speed channels eMIOS0 channels 0 7 and channels 24 31 Channels 9 15 do not support operations on internal counter...

Страница 236: ...onality across the MPC5606S family as a function of flash memory size 9 1 5 Channel Types The channels of the eMIOS200_0 and eMIOS200_1 blocks on this device are implemented using a variety of differe...

Страница 237: ...Action Output Compare X X X X X MCB Modulus Counter Buffered X X X OPWFMB Output Pulse Width and Frequency Modulation Buffered X X X OPWMB Output Pulse Width Modulation Buffered X X X Table 9 3 eMIOS...

Страница 238: ...nternal counter Prescaler Comparator A with zero detection Comparator B FSM ODISSL 0 1 EDPOL ODIS UCOUT IF 0 3 ipp_ind_mts_uc n UCPRE 0 1 UCPREN Internal counter clock See note 1 Counter bus A Counter...

Страница 239: ...MODE 25 31 The MODE 0 6 bits select the channel mode operation as shown in Table 9 5 Table 9 5 Channel mode selection MODE 0 6 1 1 b adjust parameters for the mode of operation Refer to Section 9 5 1...

Страница 240: ...put Output System Clock Prescaler system clock internal counter clock enable Output disable control Bus A CH 0 EMIOSI 0 EMIOSO 0 ipp_obe_emios_ch 0 see note 1 emios_flag_out 0 Notes 1 Connection betwe...

Страница 241: ...s which perform specific functions not included in MIOS inheritance 9 2 2 Features The basic features of the eMIOS200 on this device are the following 24 channels 16 in eMIOS200_0 and 8 in eMIOS200_1...

Страница 242: ...ilter IPF The output of the IPF is then used by the channel logic and is available to be read by the MCU through the UCIN bit of the EMIOSS n register 9 3 2 2 emioso n eMIOS200 Channel Output Signal e...

Страница 243: ...he Unified Channel memory map Table 9 7 eMIOS200 memory map eMIOS200 n Base Address Description Location 0x000 0x003 Module Configuration register EMIOSMCR on page 242 0x004 0x007 Global FLAG register...

Страница 244: ...OS200 in low power mode The MDIS bit is used to stop the clock of the block except the access to registers EMIOSMCR EMIOSOUDIS and EMIOSUCDIS 0 Clock is running 1 Enter low power mode FRZ Freeze Enabl...

Страница 245: ...ster as shown in Figure 9 6 and Figure 9 7 For Unified Channels these bits are mirrors of the FLAG bits in the EMIOSS n register Table 9 10 Global Prescaler clock divider GPRE 0 7 Divide ratio 0000000...

Страница 246: ...0 0 0 0 0 0 F23 F22 F21 F20 F19 F18 F17 F16 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0...

Страница 247: ...OUDIS field descriptions Field Description OU n Channel n Output Update Disable bit When running MCB or an output mode values are written to registers A2 and B2 OU n bits are used to disable transfers...

Страница 248: ...0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 9 11 eMIOS200 Enable Channel Register EMIOSUCDIS for EMIOS200_1...

Страница 249: ...EMIOSB register The EMIOSB register is required for the following modes OPWMB OPWFMB and MCB Address UC n base address 0x04 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0...

Страница 250: ...s OPWFMB and MCB It is possible that for particular reasons EMIOSCNT may be available on one device even if the respective channel does not feature any mode that requires it In this case EMIOSCNT avai...

Страница 251: ...in operates normally 1 If the selected Output Disable Input signal is asserted the output pin goes to EDPOL for OPWFMB and OPWMB modes and to the complement of EDPOL for other output modes but the Uni...

Страница 252: ...to a successful comparison on comparator B except that the FLAG bit is not set This bit is cleared by reset and is always read as zero This bit is valid for every output operation mode which uses com...

Страница 253: ...counter increments if phase_A is ahead of the phase_B signal Note In order to operate properly EDPOL bit must contain the same value in UC n and UC n 1 For output modes the EDPOL bit is used to select...

Страница 254: ...r bus D 10 Reserved 11 All channels internal counter Table 9 20 UC MODE bits MODE 0 6 1 1 b adjust parameters for the mode of operation Refer to Section 9 5 1 1 UC modes of operation for details Mode...

Страница 255: ...A G W w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 9 21 EMIOSS n field descriptions Field Description OVR Overrun bit The OVR bit indicates that FLAG generation occurred when the FLAG bit was a...

Страница 256: ...er bus Counter buses B C and D are the local counter buses The eMIOS200 counter buses are driven by channels in specific locations The global counter bus is driven by the channel in channel slot 23 Co...

Страница 257: ...nnel 2 memory Any attempt to access those registers will return no meaningful data and a transfer error will be generated Figure 9 18 eMIOS200 full channel configuration using Unified Channels only ch...

Страница 258: ...to the output pin eMIOS200 Status and Control register An Output Disable Input selector which selects the Output Disable Input signal that will be used as output disable Figure 9 19 Unified Channel bl...

Страница 259: ...ied Channel control and datapath block diagrams 9 5 1 1 UC modes of operation The mode of operation of the Unified Channel is determined by the mode select bits MODE 0 6 in the EMIOSC n register see F...

Страница 260: ...s could lead to invalid and unexpected output compare or input capture results or the FLAGs being set incorrectly In GPIO input mode MODE 0 6 0000000 the FLAG generation is determined according to the...

Страница 261: ...flip flop is set to the complement of the EDPOL bit in the EMIOSC n register The counter bus can be either internal or external and is selected through BSL 0 1 bits Figure 9 23 and Figure 9 24 show ho...

Страница 262: ...transitions between cycles when changing the value of the A2 register on the fly The A1 register is updated at the cycle boundary which is defined as when the internal counter transitions to 0x1 selec...

Страница 263: ...value matches the A1 value and a clock tick occurs either prescaled clock or input pin event If the up down counter is selected by setting MODE 4 1 the counter changes direction at A1 match and counts...

Страница 264: ...at the same time that the counter EMIOSCNT n is loaded with 0x1 The load signal pulse has the duration of one system clock period If A2 is written within cycle n 1 its value is available at A1 at the...

Страница 265: ...The internal channel counter is automatically selected as the time base when this mode is selected The A1 register indicates the duty cycle and the B1 register the frequency Both the A1 and B1 registe...

Страница 266: ...in transition occurs when the A1 or B1 match signal is deasserted which is indicated by the A1 match negative edge detection signal If register A1 is set to 0x4 the output pin transitions four counter...

Страница 267: ...1 and B1 register updates for synchronization purposes In Figure 9 31 it is assumed that both the channel and global prescalers are set to 0x1 each divide ratio is two meaning that the channel interna...

Страница 268: ...ls and a high to low transition at A1 match In this case EDPOL should be set to 0 Note that both the channel and global prescalers are set to 0x0 each divide ratio is one meaning that the channel inte...

Страница 269: ...op to the level corresponding to a match on comparators A or B respectively Similarly a B1 match on FORCMB sets the internal counter to 0x1 The FLAG bit is not set by the FORCMA or FORCMB bits being a...

Страница 270: ...formation about A1 and B1 register updating The FLAG bit can be generated at B1 matches when MODE 5 is cleared or in both A1 and B1 matches when MODE 5 is set If subsequent matches occur on comparator...

Страница 271: ...ge to transition the output flip flop Figure 9 35 shows the channel operation for 0 duty cycle Note that the A1 match positive edge signal occurs at the same time as the B1 0x8 negative edge signal In...

Страница 272: ...r B1 match Note that the Output Disable does not modify the FLAG bit behavior Note that there is one system clock delay between the assertion of the output disable signal and the transition of the out...

Страница 273: ...uty cycle signal is generated 9 5 1 2 Input Programmable Filter IPF The IPF ensures that only valid input pin transitions are received by the Unified Channel edge detector A block diagram of the IPF i...

Страница 274: ...as a glitch and it is not passed on to the edge detector A timing diagram of the input filter is shown in Figure 9 39 Figure 9 39 IPF example The filter is not disabled during freeze state 9 5 1 3 Cl...

Страница 275: ...istent until the channel enters GPIO mode again 9 5 2 IP Bus Interface Unit BIU The BIU provides the interface between the Internal Interface Bus IIB and the Peripheral Bus allowing communication amon...

Страница 276: ...hen interrupts are enabled the software must clear the FLAG bits before exiting the interrupt service routine 9 6 2 Application information Correlated output signals can be generated by all output ope...

Страница 277: ...ounter behaves as shown in Figure 9 42 The internal counter clears at the start of the match signal skips the next prescaled clock edge and then increments on the subsequent prescaled clock edge NOTE...

Страница 278: ...nitialization The following basic steps summarize basic output mode startup assuming the channels are initially in GPIO mode 1 global Disable the Global Prescaler 2 timebase channel Disable the Channe...

Страница 279: ...tput channel Set A B register 10 output channel Select the timebase input through the BSL 1 0 bits 11 output channel Enter the output mode 12 output channel Set the prescaler ratio same ratio as the t...

Страница 280: ...Configurable Enhanced Modular IO Subsystem eMIOS200 MPC5606S Microcontroller Reference Manual Rev 7 278 Freescale Semiconductor...

Страница 281: ...t it has a hard wired configuration 10 2 Block diagram Figure 10 1 shows a block diagram of the crossbar switch Figure 10 1 XBAR block diagram 10 3 Overview The XBAR allows for concurrent transactions...

Страница 282: ...RAM Graphics SRAM Peripheral bridge PBRIDGE QuadSPI 32 bit address 32 bit data paths Fully concurrent transfers between independent master and slave ports Fixed priority scheme and fixed parking strat...

Страница 283: ...ower priority master also makes a request to the different slave port B In this case the lower priority master is granted bus ownership of slave port B after a cycle of arbitration assuming the higher...

Страница 284: ...ich does not own the slave port is granted access after a one clock delay 10 6 5 Priority assignment Each master port is assigned a fixed 3 bit priority level hard wired priority The following table s...

Страница 285: ...level is lower than that of the master that currently has control of the slave port the new requesting master is forced to wait until the master that currently has control of the slave port is finish...

Страница 286: ...Crossbar Switch XBAR MPC5606S Microcontroller Reference Manual Rev 7 284 Freescale Semiconductor...

Страница 287: ...an external peripheral device This device implements DSPI 0 and DSPI 1 The x appended to signal names signifies the DSPI module to which the signal applies Thus CS0_0 is the CS0 signal that applies to...

Страница 288: ...se of the eDMA controller or through host software Figure 11 2 shows a DSPI with external queues in internal SRAM Figure 11 2 DSPI with queues and eDMA 11 4 Features The DSPI supports these SPI featur...

Страница 289: ...DF FIFO overrun attempt to transmit with an empty TX FIFO or serial frame received while RX FIFO is full RFOF FIFO under flow slave only and SPI mode the slave is asked to transfer data when the TX FI...

Страница 290: ...dule Disable mode The DSPI enters the Module Disable mode when the MDIS bit in DSPIx_MCR is set For more information refer to Section 11 8 1 3 Module Disable mode 11 5 4 External Stop mode The Externa...

Страница 291: ...in is used for DSPI Master mode as a chip select output set the OBE bit When the pin is used in DSPI Slave mode as a slave select input set the IBE bit 11 6 2 2 Peripheral Chip Selects 1 2 CS1 2 CS1 2...

Страница 292: ...e 0x0020 DSPIx_CTAR5 DSPI Clock and Transfer Attributes Register 5 on page 293 Base 0x0024 DSPIx_CTAR6 DSPI Clock and Transfer Attributes Register 6 on page 293 Base 0x0028 DSPIx_CTAR7 DSPI Clock and...

Страница 293: ...0 PES HALT W w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Figure 11 3 DSPI Module Configuration Register DSPIx_MCR Table 11 3 DSPIx_MCR field descriptions Field Description 0 MSTR Master Slave mode s...

Страница 294: ...reset value of the MDIS bit is parameterized with a default reset value of 0 0 Enable DSPI clocks 1 Allow external logic to disable DSPI clocks 18 DIS_TXF Disable transmit FIFO Enables and disables t...

Страница 295: ...r to Section 11 8 2 Start and stop of DSPI transfers for details on the operation of this bit 0 Start transfers 1 Stop transfers Address Base 0x0008 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12...

Страница 296: ...3 Base 0x001C DSPIx_CTAR4 Base 0x0020 DSPIx_CTAR5 Base 0x0024 DSPIx_CTAR6 Base 0x0028 DSPIx_CTAR7 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DBR FMSZ CPO L CPH A LSB FE PCSSCK PASC...

Страница 297: ...to the peripheral device interpreting the switch of clock polarity as a valid clock edge 0 The inactive state value of SCK is low 1 The inactive state value of SCK is high 6 CPHA Clock Phase The CPHA...

Страница 298: ...The PBR field selects the prescaler value for the baud rate This field is used only in Master mode The baud rate is the frequency of the Serial Communications Clock SCK The system clock is divided by...

Страница 299: ...Clock operation the DT value is fixed to one TSCK except when the TSBC bit from DSPI_DSICR register enables the TSB configuration The Delay after Transfer is a multiple of the system clock period and...

Страница 300: ...0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 Table 11 9 DSPI after SCK delay scaler ASC After SCK delay scaler value ASC After SCK delay scaler value 0000 2 1000 512 0001 4 1001 1024 00...

Страница 301: ...11 65536 Table 11 11 DSPI baud rate scaler BR Baud rate scaler value BR Baud rate scaler value 0000 2 1000 256 0001 4 1001 512 0010 6 1010 1024 0011 8 1011 2048 0100 16 1100 4096 0101 32 1101 8192 011...

Страница 302: ...ils The EOQF bit is cleared by writing 1 to it When the EOQF bit is set the TXRXS bit is automatically cleared 0 EOQ is not set in the executing command 1 EOQ bit is set in the executing SPI command N...

Страница 303: ...to the shift register 20 23 TXNXTPTR 0 3 Transmit Next Pointer Indicates which TX FIFO entry is transmitted during the next transfer The TXNXTPTR field is updated every time SPI data is transferred fr...

Страница 304: ...nables the TFFF flag in the DSPIx_SR to generate a request The TFFF_DIRS bit selects between generating an interrupt request or a DMA requests 0 TFFF interrupt requests or DMA requests are disabled 1...

Страница 305: ...ain DMA or interrupt request select Selects between generating a DMA request or an interrupt request When the RFDF flag bit in the DSPIx_SR is set and the RFDF_RE bit in the DSPIx_RSER is set the RFDF...

Страница 306: ...rovides a means for host software to signal to the DSPI that the current SPI transfer is the last in a queue At the end of the transfer the EOQF bit in the DSPIx_SR is set 0 The SPI data is not the la...

Страница 307: ...elds in the DSPI pop receive FIFO register 11 7 2 8 DSPI Transmit FIFO Registers 0 4 DSPIx_TXFRn The DSPIx_TXFRn registers provide visibility into the TX FIFO for debugging purposes Each register is a...

Страница 308: ...PIx_RXFR0 DSPIx_RXFR3 Address Base 0x003C DSPIx_TXFR0 Base 0x0040 DSPIx_TXFR1 Base 0x0044 DSPIx_TXFR2 Base 0x0048 DSPIx_TXFR3 Base 0x004C DSPIx_TXFR4 Access R O 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R...

Страница 309: ...field in the DSPIx_PUSHR The 16 bit shift register in the master and the 16 bit shift register in the slave are linked by the SOUT_x and SIN_x signals to form a distributed 32 bit register When a data...

Страница 310: ...dule Disable mode External stop mode Debug mode Master Slave and Module Disable modes are module specific modes The external stop and debug modes are device specific modes The module specific modes ar...

Страница 311: ...shut off The DSPI exits External Stop mode and resumes normal operation once the clocks are turned on Serial communications or register accesses made while in External Stop mode are ignored even if t...

Страница 312: ...ers the received data from the RX FIFO to memory external to the DSPI The FIFO buffer operations are described in Section 11 8 3 4 transmit First In First Out TX FIFO buffering mechanism and Section 1...

Страница 313: ...ion with an SPI master The SPI Slave mode transfer attributes are set in the DSPIx_CTAR0 register 11 8 3 3 FIFO disable operation The FIFO disable mechanisms allow SPI transfers without using the TX F...

Страница 314: ...to the TFFF in the DSPIx_SR The TFFF can generate a DMA request or an interrupt request Refer to Section 11 8 7 2 Transmit FIFO fill interrupt or DMA request TFFF for details The DSPI ignores attempts...

Страница 315: ...FOF bit in the DSPIx_SR is set indicating an overflow condition Depending on the state of the ROOE bit in the DSPIx_MCR the data from the transfer that generated the overflow is ignored or put in the...

Страница 316: ...CSSCK fields in the DSPIx_CTARn registers select the CS_x to SCK_x delay and the relationship is expressed by the following formula Table 11 20 shows an example of the computed CS to SCK_x delay 11 8...

Страница 317: ...clock mode the tDT delay is configurable as outlined in the DSPI_CTARx registers When in continuous clock mode and TSB is not enabled the delay is fixed at 1 SCK period When in TSB and continuous mod...

Страница 318: ...PI is the bus slave CPOL and CPHA bits in the DSPIx_CTAR0 SPI Slave mode select the polarity and phase of the serial clock Even though the bus slave does not control the SCK signal the clock polarity...

Страница 319: ...the cycle to give the peripheral more setup time The MTFE bit in the DSPIx_MCR selects between classic SPI format and modified transfer format The classic SPI formats are described in Section 11 8 5 1...

Страница 320: ...r serial data output signals For the rest of the frame the master and the slave sample their SIN_x pins on the odd numbered clock edges and change the data on their SOUT_x pins on the even numbered cl...

Страница 321: ...lave SOUT_x pin At the second edge of the SCK_x the master and slave sample their SIN_x pins For the rest of the frame the master and the slave change the data on their SOUT_x pins on the odd numbered...

Страница 322: ...signal After the CSx to SCK_x delay has elapsed the first SCK_x edge is generated The slave samples the master SOUT_x signal on every odd numbered SCK_x edge The slave also places new data on the sla...

Страница 323: ...OUT pins at the first edge of SCK The slave samples the master SOUT signal on the even numbered edges of SCK The master samples the slave SOUT signal on the odd numbered SCK edges starting with the th...

Страница 324: ...continuous selection format is enabled for the SPI configuration by setting the CONT bit in the SPI command When the CONT bit 0 the DSPI drives the asserted chip select signals to their idle states i...

Страница 325: ...ing Continuous Selection can cause errors in the transfer The PCS signal should be negated before CTAR is switched or different PCS signals are selected 11 8 5 6 Clock polarity switching between DSPI...

Страница 326: ...I is in SPI configuration CTAR0 shall be used initially At the start of each SPI frame transfer the CTAR specified by the CTAS for the frame should be CTAR0 In all configurations the currently selecte...

Страница 327: ...ONT bit in the TX FIFO entry is set CS remains asserted between the transfers when the CS signal for the next transfer is the same as for the current transfer Under certain conditions SCK can continue...

Страница 328: ...14 and Figure 11 15 that illustrate when EOQF is set 11 8 7 2 Transmit FIFO fill interrupt or DMA request TFFF The transmit FIFO fill request indicates that the TX FIFO is not full The transmit FIFO f...

Страница 329: ...F_RE bit in the DSPIx_RSER must be set for the interrupt request to be generated Depending on the state of the ROOE bit in the DSPIx_MCR the data from the transfer that generated the overflow is eithe...

Страница 330: ...ling slave interface signals from consuming power unless the DSPI is accessed 11 9 Initialization and application information 11 9 1 How to change queues DSPI queues are not part of the DSPI module bu...

Страница 331: ...aud rate prescaler PBR and the baud rate scaler BR in the DSPIx_CTARs The values are calculated at a 64 MHz system frequency with DBR 0 Table 11 26 Baud rate values Baud rate divider prescaler values...

Страница 332: ...he first in entry in each FIFO is memory mapped For the TX FIFO the first in pointer is the transmit next pointer TXNXTPTR For the RX FIFO the first in pointer is the pop next pointer POPNXTPTR Table...

Страница 333: ...ress of the last in entry in the TX FIFO is computed by the following equation Last in entry address TX FIFO base 4 x TXCTR TXNXTPTR 1 modulo TX FIFO depth where TX FIFO base base address of transmit...

Страница 334: ...Deserial Serial Peripheral Interface DSPI MPC5606S Microcontroller Reference Manual Rev 7 332 Freescale Semiconductor RX FIFO depth receive FIFO depth implementation specific...

Страница 335: ...ernal memory and displays them on a TFT LCD panel A wide range of panel sizes is supported and the timing of the interface signals is highly configurable Graphics are read directly from memory and the...

Страница 336: ...igures the graphical content of the TFT LCD panel Registers Interface control Layer0 Layer1 Layer2 Pixel Format Converter Blending Gamma Correction out FIFO Display Driver Parallel data Interface Gamm...

Страница 337: ...tion describes the characteristics of the graphics to be displayed on the panel and how they are blended together The DCU manages the graphical content of the panel through sets of registers called la...

Страница 338: ...and chroma key blending modes Transparency modes for anti aliased text and graphics Luminance mode for highlighting content Tile mode for efficient creation of textured background content 12 1 3 Modes...

Страница 339: ...T Pixel clock used to drive the display panel dcu_vsync OUT Vertical sync signal indicating the beginning of a new frame dcu_hsync OUT Horizontal sync signal indicating the beginning of a new line dcu...

Страница 340: ...Table 12 3 DCU register map Address offset Register Access Reset value Location General registers 0x000 CtrlDescL0_1 Register R W 0x00000000 on page 353 0x004 CtrlDescL0_2 Register R W 0x00000000 on...

Страница 341: ...0x00000000 on page 353 0x074 CtrlDescL4_2 Register R W 0x00000000 on page 354 0x078 CtrlDescL4_3 Register R W 0x00000000 on page 355 0x07C CtrlDescL4_4 Register R W 0x00000000 on page 356 0x080 CtrlDe...

Страница 342: ...00000 on page 359 0x0F8 CtrlDescL8_7 Register R W 0x00000000 on page 361 0x0FC CtrlDescL9_1 Register R W 0x00000000 on page 353 0x100 CtrlDescL9_2 Register R W 0x00000000 on page 354 0x104 CtrlDescL9_...

Страница 343: ...0000000 on page 356 0x17C CtrlDescL13_5 Register R W 0x00000000 on page 358 0x180 CtrlDescL13_6 Register R W 0x00000000 on page 359 0x184 CtrlDescL13_7 Register R W 0x00000000 on page 361 0x188 CtrlDe...

Страница 344: ...page 377 0x200 COLBAR_4 Register R W 0xFF00FF00 on page 377 0x204 COLBAR_5 Register R W 0xFFFFFF00 on page 378 0x208 COLBAR_6 Register R W 0xFFFF0000 on page 378 0x20C COLBAR_7 Register R W 0xFFFF00FF...

Страница 345: ...0000000 on page 393 0x284 FG6_bcolor Register R W 0x00000000 on page 394 0x288 FG7_fcolor Register R W 0x00000000 on page 393 0x28C FG7_bcolor Register R W 0x00000000 on page 394 0x290 FG8_fcolor Regi...

Страница 346: ...YNC PARA R W 0x00000000 on page 400 0x314 Soft Lock Bit Register POL R W 0x00000000 on page 401 0x318 Soft Lock Bit Register L0_TRANSP R W 0x00000000 on page 401 0x31C Soft Lock Bit Register L1_TRANSP...

Страница 347: ...0 0 0 TILE_HOR_SIZE W CtrlDescCurs or_1 0x1C0 R 0 0 0 0 0 0 HEIGHT W R 0 0 0 0 0 0 WIDTH W CtrlDescCurs or_2 0x1C4 R 0 0 0 0 0 0 POSY W R 0 0 0 0 0 0 POSX W CtrlDescCurs or_3 0x1C8 R CU R_E N 0 0 0 0...

Страница 348: ...D4 R 0 0 0 0 0 0 0 0 BGND_R W R BGND_G BGND_B W DISP_SIZE 0x1D8 R 0 0 0 0 0 0 DELTA_Y W R 0 0 0 0 0 0 0 0 DELTA_X W HSYN_PARA 0x1DC R 0 BP_H 0 0 PW_H 0 3 W R PW_H 4 8 0 0 FP_H W VSYN_PARA 0x1E0 R 0 BP...

Страница 349: ...RFLOW CRC_READY VS_BLANK LS_BF_VS UNDRUN VSYNC W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c INT_MASK 0x1F0 R 0 0 0 0 0 0 0 0 0 0 0 0 M_P4_FIFO_HI_FLAG M_P4_FIFO_LO_FLAG M_P3_FIFO_HI_FLAG M_P3...

Страница 350: ..._4_B W COLBAR_5 0x204 R 1 1 1 1 1 1 1 1 COLBAR_5_R W R COLBAR_5_G COLBAR_5_B W COLBAR_6 0x208 R 1 1 1 1 1 1 1 1 COLBAR_6_R W R COLBAR_6_G COLBAR_6_B W COLBAR_7 0x20C R 1 1 1 1 1 1 1 1 COLBAR_7_R W R C...

Страница 351: ...0 0 0 PDI_BLANKING_ERR PDI_ECC_ERR2 PDI_ECC_ERR1 PDI_LOCK_LOST PDI_LOCK_DET PDI_VSYNC_DET PDI_HSYNC_DET PDI_DE_DET PDI_CLK_LOST PDI_CLK_DET W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Mask_PDI_S TATUS 0...

Страница 352: ...US 0x230 R 0 0 0 0 0 0 0 0 0 0 0 0 0 M_HWC_ERR M_SIG_ERR M_DISP_ERR W R M_L15_PARR_ERR M_L14_PARR_ERR M_L13_PARR_ERR M_L12_PARR_ERR M_L11_PARR_ERR M_L10_PARR_ERR M_L9_PARR_ERR M_L8_PARR_ERR M_L7_PARR_...

Страница 353: ...0 0 0 0 Cr_BLUE W R 0 0 0 0 Cb_BLUE W CRC_POS 0x24c R CRC_POS W R W FGx_fcolor 0x250 R 1 1 1 1 1 1 1 1 FGX_FCOLOR 0 7 W R FGX_FCOLOR 8 23 W FGx_bcolor 0x254 R 1 1 1 1 1 1 1 1 FGX_BCOLOR 0 7 W R FGX_B...

Страница 354: ..._L1_7 0 W WEN_L1_1 WEN_L1_2 WEN_L1_3 WEN_L1_4 WEN_L1_5 WEN_L1_6 WEN_L1_7 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Soft_Lock_DI SP_SIZE 0x30c R 0 0 0 0 SLB_DISP 0 0 0 0 0 0 0 0 0 0 0 W WEN_DISP R 0 0 0 0 0...

Страница 355: ...s register sets the height and width of the layer associated with the register Soft_Lock L0_TRANSP 0x318 R 0 0 0 0 SLB_FCOLOR SLB_BCOLOE 0 0 0 0 0 0 0 0 0 0 W WEN_FCOLOR WEN_BCOLOR R 0 0 0 0 0 0 0 0 0...

Страница 356: ...1 0x16C CtrlDescL13_1 0x188 CtrlDescL14_1 0x194 CtrlDescL15_1 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 HEIGHT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 2...

Страница 357: ...DescL5_2 0x0AC CtrlDescL6_2 0x0C8 CtrlDescL7_2 0x0E4 CtrlDescL8_2 0x100 CtrlDescL9_2 0x11C CtrlDescL10_2 0x138 CtrlDescL11_2 0x154 CtrlDescL12_2 0x170 CtrlDescL13_2 0x18C CtrlDescL14_2 0x198 CtrlDescL...

Страница 358: ...0x078 CtrlDescL4_3 0x094 CtrlDescL5_3 0x0b0 CtrlDescL6_3 0x0CC CtrlDescL7_3 0x0E8 CtrlDescL8_3 0x104 CtrlDescL9_3 0x120 CtrlDescL10_3 0x13C CtrlDescL11_3 0x158 CtrlDescL12_3 0x174 CtrlDescL13_3 0x18C...

Страница 359: ...19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 LUOFFS 0 BB AB W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 8 CtrlDescL0_4 field descriptions Field Description 0 EN Enable the layer 0 OFF 1 ON 1 TILE_E...

Страница 360: ...24 bpp 0110 32 bpp ARGB8888 0111 Transparency mode 4 bpp 1000 Transparency mode 8bpp 1001 Luminance offset mode 4 bpp 1010 Luminance offset mode 8 bpp 1011 16 bpp ARGB1555 1100 16 bpp ARGB4444 1101 1...

Страница 361: ...5 0x080 CtrlDescL4_5 0x09C CtrlDescL5_5 0x0B8 CtrlDescL6_5 0x0D4 CtrlDescL7_5 0x0F0 CtrlDescL8_5 0x10C CtrlDescL9_5 0x128 CtrlDescL10_5 0x144 CtrlDescL11_5 0x160 CtrlDescL12_5 0x17C CtrlDescL13_5 0x19...

Страница 362: ..._6 0x148 CtrlDescL11_6 0x164 CtrlDescL12_6 0x180 CtrlDescL13_6 0x198 CtrlDescL14_6 0x1B8 CtrlDescL15_6 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 CKMIN_R W Reset 0...

Страница 363: ...x050 CtrlDescL2_7 0x06C CtrlDescL3_7 0x088 CtrlDescL4_7 0x094 CtrlDescL5_7 0x0C0 CtrlDescL6_7 0x0DC CtrlDescL7_7 0x0F8 CtrlDescL8_7 0x114 CtrlDescL9_7 0x130 CtrlDescL10_7 0x14C CtrlDescL11_7 0x168 Ctr...

Страница 364: ...0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 HEIGHT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 WIDTH W Reset 0 0 0 0 0 0 0 0 0 0 0 0...

Страница 365: ...ions Field Description 6 15 POSY Y position of the cursor in pixels 22 31 POSX X position of the cursor in pixels Offset 0x1C8 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CUR _EN DE...

Страница 366: ...0 0 0 0 HWC_BLINK_OFF W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 EN_BLINK HWC_BLINK_ON W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 15...

Страница 367: ...D_ITER Defines the number of planes used for blending 010 Two plane blending 011 Three plane blending 100 Four plane blending All other values two plane blending is selected and BLEND_ITER is set to 2...

Страница 368: ...de 0 Disabled 1 Enabled 25 TAG_EN Enables the calculation of CRC only on the safety layers 0 CRC calculated over the whole area of interest area of interest given by SIG_DESC registers 1 Calculates CR...

Страница 369: ...W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 17 BGND field descriptions Field Description 8 15 BGND_R Red component of the default color displayed in the sectors where no layer is active 16 23 BGN...

Страница 370: ...VSYNC signal front porch back porch and active pulse width respectively Table 12 18 DISP_SIZE field descriptions Field Description 6 15 DELTA_Y Sets the display size vertical resolution in pixels 24...

Страница 371: ...25 26 27 28 29 30 31 R PW_V 4 8 0 0 FP_V W Reset 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 Table 12 20 VSYN_PARA field descriptions Field Description 1 9 BP_V VSYNC back porch pulse width in horizontal line cy...

Страница 372: ...Display samples data on the falling edge 1 Display samples data on the rising edge 26 NEG Indicates if value at the output pixel data output needs to be negated 0 Output is to remain same 1 Output to...

Страница 373: ...BF_VS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R OUT_BUF_HIGH OUT_BUF_LOW W Reset 0 1 1 1 1 0 0 0 0 0 0 0 1 0 1 0 Table 12 22 Threshold Register field de...

Страница 374: ...HI_FLAG Interrupt signal that indicates the High threshold has been reached for plane 4 FG2plane input buffer 13 P4_FIFO_LO_FLAG Interrupt signal that indicates the Low threshold has been reached for...

Страница 375: ...s done and ready to be compared with precomputed CRC value by the software 28 VS_BLANK Interrupt signal to indicate vertical blanking period This is the period in which all the registers that affect t...

Страница 376: ...OW M_CRC_READY M_VS_BLANK M_LS_BF_VS M_UNDRUN M_VSYNC W Reset 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Table 12 24 INT_MASK field descriptions Field Description 12 M_P4_FIFO_HI_FLAG P4_FIFO_HI_FLAG interrupt m...

Страница 377: ...0 Interrupt is not masked 1 Interrupt is masked 25 M_P1_FIFO_LO_FLAG P1_FIFO_LO_FLAG interrupt mask 0 Interrupt is not masked 1 Interrupt is masked 26 M_CRC_OVERFLOW CRC_OVERFLOW interrupt mask 0 Inte...

Страница 378: ...3 4 5 6 7 8 9 10 11 12 13 14 15 R 1 1 1 1 1 1 1 1 COLBAR_1_R W Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R COLBAR_1_G COLBAR_1_B W Reset 0 0 0 0 0 0 0 0 0...

Страница 379: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 1 1 1 1 1 1 1 1 COLBAR_3_R W Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R COLBAR_3_G COLBAR_3_B W Reset 1 1 1 1 1 1 1 1...

Страница 380: ...1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 1 1 1 1 1 1 1 1 COLBAR_5_R W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R COLBAR_5_G COLBAR_5_B W Reset 1 1 1 1 1 1 1 1...

Страница 381: ...gister Offset 0x20C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 1 1 1 1 1 1 1 1 COLBAR_7_R W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R...

Страница 382: ...0 1 1 1 1 1 Table 12 26 DIV_RATIO field descriptions Field Description 24 31 DIV_RATIO Specifies the divide value for the input clock Used to generate the pixel clock to support different types of dis...

Страница 383: ...14 15 R 0 0 0 0 0 0 SIG_VER_POS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 SIG_HOR_POS W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 28 SI...

Страница 384: ...ET PDI_HSYNC_DET PDI_DE_DET PDI_CLK_LOST PDI_CLK_DET W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 30 PDI Status Register field descriptions Field Descriptio...

Страница 385: ...i_de_det Status bit to inform the software that data Enable for the camera data has been detected 0 pdi_de not detected 1 pdi_de is detected 30 pdi_clk_lost Status bit to inform the software that pdi_...

Страница 386: ...eld descriptions Field Description 22 m_pdi_blanking_er r pdi_blanking_err interrupt mask 0 Interrupt is not masked 1 Interrupt is masked 23 m_pdi_ecc_err2 pdi_ecc_err2 interrupt mask 0 Interrupt is n...

Страница 387: ..._ERR L14_PARR_ERR L13_PARR_ERR L12_PARR_ERR L11_PARR_ERR L10_PARR_ERR L9_PARR_ERR L8_PARR_ERR L7_PARR_ERR L6_PARR_ERR L5_PARR_ERR L4_PARR_ERR L3_PARR_ERR L2_PARR_ERR L1_PARR_ERR L0_PARR_ERR W w1c w1c...

Страница 388: ...meter error is not set 1 Parameter error is set 23 L08_PARR_ERR Interrupt occurs whenever there is an error in layer 8 0 Parameter error is not set 1 Parameter error is set 24 L7_PARR_ERR Interrupt oc...

Страница 389: ...0 0 0 0 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R M_L15_parr_err M_L14_parr_err M_L13_parr_err M_L12_parr_err M_L11_parr_err M_L10_parr_err M_L9_parr_err M_L8_parr_err M_L7_parr_err M_L6...

Страница 390: ...rrupt mask 0 Do not mask the interrupt 1 Mask the interrupt 23 M_L8_parr_err M_L8_parr_err interrupt mask 0 Do not mask the interrupt 1 Mask the interrupt 24 M_L7_parr_err M_L7_parr_err interrupt mask...

Страница 391: ...rrupt 1 Mask the interrupt Offset 0x234 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R INP_BUF_p2_hi INP_BUF_p2_lo W Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25...

Страница 392: ...INP_BUF_p3_hi INP_BUF_p3_lo W Reset 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Table 12 35 THRESHOLD_INP_BUF_2 field descriptions Field Description 0 7 INP_BUF_p4_hi High Threshold for input buffer for blend st...

Страница 393: ...riptions Field Description 0 9 Y_RED Luminance Coefficient for Red Matrix 11 20 Y_GREEN Luminance Coefficient for Green Matrix 22 31 Y_BLUE Luminance Coefficient for Blue Matrix Offset 0x240 Access Us...

Страница 394: ...0 Cr_GREEN W Reset 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 Cb_GREEN W Reset 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 0 Table 12 38 Green Chroma Component Regist...

Страница 395: ...d descriptions Field Description 5 15 Cr_BLUE Cr Coefficient for Blue Matrix 20 31 Cb_BLUE Cb Coefficient for Blue Matrix Offset 0x24C Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R CR...

Страница 396: ...0x288 FG7_FCOLOR 0x290 FG8_FCOLOR 0x298 FG9_FCOLOR 0x2A0 FG10_FCOLOR 0x2A8 FG11_FCOLOR 0x2B0 FG12_FCOLOR 0x2B8 FG13_FCOLOR 0x2C0 FG14_FCOLOR 0x2C8 FG15_FCOLOR Access User read write 0 1 2 3 4 5 6 7 8...

Страница 397: ...0x2BC FG13_BCOLOR 0x2C4 FG14_BCOLOR 0x2CC FG15_BCOLOR Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 FG0_BCOLOR 0 7 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19...

Страница 398: ...3 SLB_L0_4 0 0 0 0 SLB_L0_5 SLB_L0_6 SLB_L0_7 0 W WEN_LO_1 WEN_LO_2 WEN_LO_3 WEN_LO_4 WEN_LO_5 WEN_LO_6 WEN_LO_7 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R...

Страница 399: ...ed protected register is locked for write access 8 WEN_L0_5 Write Enable for Soft Lock Bit SLB_L0_5 0 SLB is not modified 1 Value is written to SLB 9 WEN_L0_6 Write Enable for Soft Lock Bit SLB_L0_6 0...

Страница 400: ..._L1_3 Write Enable for Soft Lock Bit SLB_L1_3 0 SLB is not modified 1 Value is written to SLB 3 WEN_L1_4 Write Enable for Soft Lock Bit SLB_L1_4 0 SLB is not modified 1 Value is written to SLB 4 SLB_L...

Страница 401: ...ccess 13 SLB_L1_6 Soft Lock Bit for Control Desc L1_6 Register 0 Associated protected register is not locked and writeable 1 Associated protected register is locked for write access 14 SLB_L1_7 Soft L...

Страница 402: ...User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 SLB_HSYNC SLB_VSYNC 0 0 0 0 0 0 0 0 0 0 W WEN_HSYNC WEN_VSYNC Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27...

Страница 403: ...7 8 9 10 11 12 13 14 15 R 0 0 0 0 SLB_POL 0 0 0 0 0 0 0 0 0 0 0 W WEN_POL Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Rese...

Страница 404: ...0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 12 49 Soft Lock L0_TRANSP Register field descriptions Field Description 0 WEN_L0_FCOLO R Write Enable for Soft Lock Bit SLB_L0_FCOLOR...

Страница 405: ...write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 SLB_L1_FCOLOR SLB_L1_BCOLOR 0 0 0 0 0 0 0 0 0 0 W WEN_L1_FCOLOR WEN_L1_BCOLOR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25...

Страница 406: ...tion of these signals Timing diagrams for TFT LCD panels are typically divided into a horizontal timing chart and a vertical timing chart See Figure 12 56 for details Figure 12 56 HSYNC and VSYNC timi...

Страница 407: ...ng the fields in the VSYN_PARA register VSYNC provides a pulse to give the panel notice that the next frame of pixel data lines is about to start and the panel defines delays before and after this pul...

Страница 408: ...and displays graphics according to the configuration of its layers The BGND register sets the RGB color of the background shown when no other layers are present This background color is included in th...

Страница 409: ...ity The priority is used by the DCU to define how to blend individual pixels within the layers For example if layer 0 is defined as not being blended with other layers and a pixel on layer 0 overlaps...

Страница 410: ...ap each other Figure 12 58 shows the individual source graphics and the case where no layer has any blending enabled Here the highest priority layer in this case layer 0 is fully visible Layer 1 is vi...

Страница 411: ...blended with pixels in the underlying layers In particular note region A where layer 0 is blended with layer 4 and the background color This blending effect is repeated across all of the layers howev...

Страница 412: ...re the PROG_END bit in the INT_STATUS register is asserted 12 4 5 3 Layer size and positioning The size of each layer is defined by register 1 in the control descriptor for the layer CTRLDESCLn_1 wher...

Страница 413: ...CU The format of the data that describes the graphic is defined by the BPP bit field in register 4 in the control descriptor for the layer CTRLDESCLn_4 where n is the layer number This value also infl...

Страница 414: ...4 and the CLUT is the RAM block dedicated to the DCU which is described in Section 12 4 7 CLUT Tile RAM Since the RGB values stored in the CLUT are 24 bit RGB there is no need for further adjustment...

Страница 415: ...5 Depending on the priority and placement of the layer see Table 12 56 Data Layout for 8 bpp Address offset 7 0 15 8 23 16 31 24 0x00 pixel0 7 0 pixel1 7 0 pixel2 7 0 pixel3 7 0 0x04 pixel4 7 0 pixel5...

Страница 416: ...selected pixels are blended By combining this control with the BB bit field it is possible to define 11 unique ways of blending the pixels on a layer dependent on the type of layer Depending on the co...

Страница 417: ...nel of the selected pixels on the layer 5 0 10 RGB Same as case 3 6 1 10 RGB Selected pixels are completely removed and the value in TRANS becomes the alpha channel of the non selected pixels on the l...

Страница 418: ...Display Control Unit DCU MPC5606S Microcontroller Reference Manual Rev 7 416 Freescale Semiconductor Figure 12 60 Case 1 example no blend Figure 12 61 Case 2 example remove selected pixels...

Страница 419: ...lay Control Unit DCU MPC5606S Microcontroller Reference Manual Rev 7 Freescale Semiconductor 417 Figure 12 62 Case 3 example all pixels transparent Figure 12 63 Case 4 example selected pixels transpar...

Страница 420: ...l Unit DCU MPC5606S Microcontroller Reference Manual Rev 7 418 Freescale Semiconductor Figure 12 64 Case 6 example selected pixels removed others transparent Figure 12 65 Case 9 example no blend pixel...

Страница 421: ...t DCU MPC5606S Microcontroller Reference Manual Rev 7 Freescale Semiconductor 419 Figure 12 66 Case 10 example selected pixels removed pixel alpha ignored Figure 12 67 Case 13 example pixel and layer...

Страница 422: ...hic The DCU creates the final graphic by pre blending a foreground color and background color using the alpha value of each pixel The result of this pre blend can then be blended with pixels on other...

Страница 423: ...g pixels are obscured 2 1 00 Transparency Reserved 3 0 01 Transparency The value in TRANS becomes the alpha channel of all pixels on the layer 4 1 01 Transparency The value in TRANS becomes the alpha...

Страница 424: ...lay Control Unit DCU MPC5606S Microcontroller Reference Manual Rev 7 422 Freescale Semiconductor Figure 12 70 Case 3 example all pixels transparent Figure 12 71 Case 4 example selected pixels transpar...

Страница 425: ...re added to each component of the underlying pixel The 4 bpp mode is left shifted to form a signed 8 bpp integer The results of the addition are prevented from overflowing so that any result greater t...

Страница 426: ...raphic can be in any previously described data format See Figure 12 73 for an example of a layer in tile mode Figure 12 73 Tile mode When DATA_SEL is set to use CLUT TILE RAM the LUOFFS bitfield defin...

Страница 427: ...gister 2 in the control descriptor for the cursor CTRLDESCCURSOR _2 The register contains two bit fields POSY and POSX which determine the location of the upper left pixel of the cursor in the x and y...

Страница 428: ...er control descriptor defines the starting address of the area and the BPP and TILE_EN bit fields define what type of use the RAM area has In Figure 12 74 three areas of the RAM are defined for differ...

Страница 429: ...onent Eqn 12 5 The table is arranged as three separate memory blocks within the DCU memory map one for each of the three color components Each memory block has one entry for every possible 8 bit value...

Страница 430: ...ext vertical blanking period The DMA_TRANS_FINISH flag indicates that the DCU has completed fetching all data from memory in the current panel refresh cycle This normally precedes the vertical blankin...

Страница 431: ...D register The upper threshold is set by the OUT_BUF_HIGH bit field and this indicates that sufficient data exists in the output buffer and processing should stop until the DCU uses some of the values...

Страница 432: ...ositioning The DISP_ERR flag indicates that the VSYNC and HSYNC pulse widths are configured to the invalid value of 0 The HWC_ERR flag indicates that the hardware cursor is either larger than the avai...

Страница 433: ...scheme provides a mechanism to protect certain registers in the DCU from being written 12 6 1 Operation of scheme The register protection scheme provides a two step protection scheme for the protecte...

Страница 434: ...disabled if layer has safety mode enabled A signature calculator module is implemented in the DCU that calculates the signature value and position for a predefined area of the frame DCU specifies a s...

Страница 435: ...put signals 1 CRC is calculated when Safety mode is enabled 2 CRC can be calculated over full screen as shown in Figure 12 77 Here tag bit generated internal to DCU and flow along the data path is set...

Страница 436: ...g mode Figure 12 77 Safety mode enabled for part of the screen 4 CRC can be calculated only for the safety layers Layer 0 and 1 can only act as a safety layer Both of them have a separate control bits...

Страница 437: ...nitial value as 32 h000000000 CRC does not support Any modification of input bytes Any modification of the output CRC value before reporting When PDI is enabled with the Layer 0 and 1 safety enabled i...

Страница 438: ...t Tag bit to 1 4 Set Program Safety mode to 1 5 Check the CRC when CRC calculation interrupt is raised fora particular screen 12 8 Parallel Data Interface Camera Interface Figure 12 79 Camera interfac...

Страница 439: ...anking period The V bit is set to 1 to denote the beginning of the vertical blanking period The F bit is used for interlaced video to denote if the forthcoming line is odd or even The remaining 4 bits...

Страница 440: ...he control information from the video data The machine checks the video data for the Preamble Field 0xFF 0x00 0x00 and then depending on the status bits XY decides if it has received a valid control s...

Страница 441: ...oming clock does not have to bear any relation to the DCU clock Prior to the lock condition the DCU will run on the internal DCU clock After lock has been achieved the DCU will switch to the clock fro...

Страница 442: ...ax input frequency of 64 MHz in 8 bit muxed Narrow mode External Synchronization using Hsync Vsync and Pdi_clk External Synchronization using Hsync Vsync DataEn and pdi_clk Internal synchronization us...

Страница 443: ...565 16 bit PDI interface PDI 15 11 R 4 0 PDI 10 5 G 5 0 PDI 4 0 B 4 0 Narrow 8 bit PDI interface RGB565 In first clock cycle PDI 7 0 R 4 0 G 5 3 In second clock cycle PDI 7 0 G 2 0 B 4 0 YCbCr In firs...

Страница 444: ...width Front and back porch values should be picked from those programmed in DCU registers In order to achieve lock it must have same value as that of TFT screen Front porch and back porch value can be...

Страница 445: ...ed to decode the vertical and horizontal blanking period Table 12 68 XYh Value Bit Value Description 7 1 b1 Always 1 b1 This is checked while decoding sync preamble 6 F Not considered in the state mac...

Страница 446: ...line active All Vertical and horizontal parameter values are validated against the DCU registers programmed by the user Polarity of hsync and vsync are selectable Horizontal blanking and vertical blan...

Страница 447: ...sing function converts the stream to RGB888 RGB565 The RGB pixel value is computed using following equations Eqn 12 6 Eqn 12 7 Eqn 12 8 Note that the first multiplication i e y 16 ycoeff is unsigned T...

Страница 448: ...is coming in 1 clocks 16 bit RGB565 16 bit input data each pixel info is coming in 1 clocks 18 bit RGB666 18 bit input data each pixel info is coming in 1 clocks 16 bit RGB565 8 bit input data each pi...

Страница 449: ...tivity detection interrupts It would be generated from the state machine Vsync activity detection interrupts It would also be generated from the state machine Activity detection interrupt for data ena...

Страница 450: ...ection of all pixels on a panel Gamut The set of colors that a panel can display In most cases a panel cannot display the full gamut of colors visible to the human eye Indexed color An index into a ta...

Страница 451: ...to 16 DMA channels This is illustrated in Figure 13 1 Figure 13 1 DMACHMUX block diagram 13 1 2 Features The DMACHMUX provides these features 48 peripheral slots four always on slots can be routed to...

Страница 452: ...letely transparent to the system Periodic Trigger mode In this mode a DMA source may only request a DMA transfer such as when a transmit buffer becomes empty or a receive buffer becomes full periodica...

Страница 453: ...CHCONFIG n Table 13 2 CHCONFIGxx field descriptions Field Description ENBL DMA Channel Enable ENBL enables the DMA Channel 0 DMA channel is disabled This mode is primarily used during configuration of...

Страница 454: ...X request assignments DMA requesting module DMACHMUX source number ipd_ref_peripher Nperiphs 1 Channel Disable1 0 DSPI_0 TX 1 DSPI_0 RX 2 DSPI_1 TX 3 DSPI_1 RX 4 QuadSPI_0 TFFF 5 QuadSPI_0 RFDF RBDF 6...

Страница 455: ...00_1_FLAG_F3 34 eMIOS200_1_FLAG_F4 35 eMIOS200_1_FLAG_F5 36 eMIOS200_1_FLAG_F6 37 eMIOS200_1_FLAG_F7 38 Reserved 39 Reserved 40 Reserved 41 Reserved 42 Reserved 43 Reserved 44 Reserved 45 Reserved 46...

Страница 456: ...c triggering capability Besides the normal routing functionality the first four channels of the DMA Mux provide a special periodic triggering capability that can be used to provide an automatic mechan...

Страница 457: ...ux triggered channels The DMA channel triggering capability allows the system to schedule regular DMA transfers usually on the transmit side of certain peripherals without the intervention of the proc...

Страница 458: ...to transfer receive data into memory effectively implementing a method to periodically read data from external devices and transfer the results into memory without processor intervention Using the GP...

Страница 459: ...determining the load that the DMA transfer will incur on the system For this option the DMA channel should be disabled in the DMA channel mux Use explicit software re activation In this option the DMA...

Страница 460: ...MAMUX_BASE_ADDR 0x0003 volatile unsigned char CHCONFIG4 volatile unsigned char DMAMUX_BASE_ADDR 0x0004 volatile unsigned char CHCONFIG5 volatile unsigned char DMAMUX_BASE_ADDR 0x0005 volatile unsigned...

Страница 461: ...d char DMAMUX_BASE_ADDR 0x0006 volatile unsigned char CHCONFIG7 volatile unsigned char DMAMUX_BASE_ADDR 0x0007 volatile unsigned char CHCONFIG8 volatile unsigned char DMAMUX_BASE_ADDR 0x0008 volatile...

Страница 462: ...FIG2 volatile unsigned char DMAMUX_BASE_ADDR 0x0002 volatile unsigned char CHCONFIG3 volatile unsigned char DMAMUX_BASE_ADDR 0x0003 volatile unsigned char CHCONFIG4 volatile unsigned char DMAMUX_BASE_...

Страница 463: ...ic instructions that execute in the core operate on data in the general purpose registers GPRs Instead of the base PowerPC Book E instruction set support the e200z0h core only implements the VLE varia...

Страница 464: ...is performed to accelerate certain taken branches in the e200z0h Prefetched instructions are placed into an instruction buffer with 4 entries in e200z0h each capable of holding a single 32 bit instru...

Страница 465: ...up to two 16 bit VLE instructions per clock Instruction buffer with 4 entries in e200zh0 each holding a single 32 bit instruction or a pair of 16 bit instructions CPU CONTROL LOGIC LOAD DATA NEXUS DE...

Страница 466: ...ns 32 bit effective address adder for data memory address calculations Pipelined operation supports throughput of one load or store operation per cycle 32 bit interface to memory dedicated memory inte...

Страница 467: ...ore instructions only Figure 14 2 and Figure 14 3 show the e200 register set including the registers which are accessible while in supervisor mode and the registers which are accessible in user mode T...

Страница 468: ...are DAC1 DAC2 SPR 316 SPR 317 1 These e200 specific registers may not be supported by other PowerPC processors 2 Optional registers defined by the PowerPC Book E architecture 3 Read only registers Pro...

Страница 469: ...ated For the mtspr instruction if the SPR specified is read only and not privileged an illegal instruction exception is generated If the SPR specified is read only and privileged and the core is in us...

Страница 470: ...e200z0h Core MPC5606S Microcontroller Reference Manual Rev 7 468 Freescale Semiconductor...

Страница 471: ...troduction The DMA Direct Memory Access is a second generation platform module capable of performing complex data transfers with minimal intervention from a host processor via n programmable channels...

Страница 472: ...orting 16 32 and 64 channel implementations dependent on size of the TCD memory and design parameters Connections to the AMBA AHB crossbar switch for bus mastering the data movement slave bus for prog...

Страница 473: ...methods one service request per execution of the minor loop is required Support for fixed priority and round robin channel arbitration Channel completion reported via optional interrupt requests One...

Страница 474: ...biter beginning major iteration count unsigned intbwc 2 bandwidth control unsigned intmajor linkch 6 link channel number unsigned intdone 1 channel done unsigned intactive 1 channel executing unsigned...

Страница 475: ...sing associated with the error handling is omitted the given DMAchannel is requesting service by the software assertion of the tcd channel start bit the assertion of an enabled ipd_req from a device o...

Страница 476: ..._size bytes from the source if the ssize dsize do multiple reads to equal the dsize if the ssize dsize do a single read of source data number_of_source_reads xfer_size src_xfer_size for number_of_sour...

Страница 477: ..._mode higher_pri_request current_channel_is_preempt service_preempt_channel the bandwidth control field determines when the next read write occurs if dma_engine bwc 1 stall_dma_engine 1 dma_engine bwc...

Страница 478: ...etected abort the channel dma_engine error_status error_type record the error dma_engine active 0 clear the channel busy flag check for interrupt assertion on error if dma_engine int_err generate_inte...

Страница 479: ...gh DMAERRH Channels 63 32 0x002C DMA Error Low DMAERRL Channels 31 00 0x0030 DMA Hardware Request Status High DMAHRSH Channels 63 32 0x0034 DMA Hardware Request Status Low DMAHRSL Channels 31 00 0x003...

Страница 480: ...ies are assigned in the GRPnPri registers All group priorities must have unique values prior to any channel service requests occur otherwise a configuration error will be reported Unused group priorit...

Страница 481: ...ctor When minor loop mapping is disabled DMACR EMLM 0 all 32 bits of TCDn word2 are assigned to the nbytes field See Section 15 3 1 18 Transfer Control Descriptor TCD for more details See Figure 15 2...

Страница 482: ...t channel has a minor loop channel link enabled and the link channel is itself This effectively applies the minor loop offsets and restarts the next minor loop HALT Halt DMA Operations 0 Normal operat...

Страница 483: ...nk configuration error is reported when the link operation is serviced at minor loop completion If a system bus read or write is terminated with an error the data transfer is stopped and the appropria...

Страница 484: ...ing a valid error exists that has not been cleared ECX Transfer cancelled 0 No cancelled transfers 1 The last recorded entry was a cancelled transfer via the error cancel transfer input GPE Group Prio...

Страница 485: ...TCD dsize NCE Nbytes Citer Configuration Error 0 No nbytes citer configuration error 1 The last recorded error was a configuration error detected in the TCD nbytes or TCD citer fields TCD nbytes is no...

Страница 486: ...EI registers are provided so that the error interrupt enable for a single channel can easily be modified without the need to perform a read modify write sequence to the DMAEEI H L registers Both the D...

Страница 487: ...4 EEI 53 EEI 52 EEI 51 EEI 50 EEI 49 EEI 48 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R EEI 47 EEI 46 EEI 45 EEI 44 EEI 43 EEI 42 EEI 41 EEI 40 EEI 39 EEI...

Страница 488: ...ster provides a simple memory mapped mechanism to set a given bit in the DMAEEI H L registers to enable the error interrupt for a given channel The data value on a register write causes the correspond...

Страница 489: ...e zeroed disabling all DMA request inputs If bit 0 NOP is set the command is ignored This allows multiple byte registers to be written as a 32 bit word Reads of this register return all zeroes See Fig...

Страница 490: ...R H L registers to disable the error condition flag for a given channel The given value on a register write causes the corresponding bit in the DMAERR H L register to be cleared A data value of 64 to...

Страница 491: ...register write causes the DONE bit in the corresponding Transfer Control Descriptor to be cleared A data value of 64 to 127 regardless of the number of implemented channels provides a global clear fun...

Страница 492: ...bit position clears the corresponding channel s interrupt request A zero in any bit position has no effect on the corresponding channel s current interrupt status The DMACINT register is provided so...

Страница 493: ...The contents of this register can also be polled and a non zero value indicates the presence of a channel error regardless of the state of the DMAEEI register The state of any given channel s error i...

Страница 494: ...ERR 56 ERR 55 ERR 54 ERR 53 ERR 52 ERR 51 ERR 50 ERR 49 ERR 48 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ERR 47 ERR 46 ERR 45 ERR 44 ERR 43 ERR 42 ERR...

Страница 495: ...HRS 43 HRS 42 HRS 41 HRS 40 HRS 39 HRS 38 HRS 37 HRS 36 HRS 35 HRS 34 HRS 33 HRS 32 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 15 20 DMA Hardware Request Status High DMAHRSH register Address Base...

Страница 496: ...preempted channel is restored and resumes execution After the restored channel completes one read write sequence it is again eligible for preemption If any higher priority channel is requesting servi...

Страница 497: ...el n can be temporarily suspended by the service request of a higher priority channel DPA Disable Preempt Ability 0 Channel n can suspend a lower priority channel 1 Channel n cannot suspend any channe...

Страница 498: ...n Word 1 TCDn soff smod ssize dmod dsize fields Table 15 21 TCDn Word 1 TCDn smod ssize dmod dsize soff field descriptions Name Description smod 0 4 Source address modulo 0 Source address modulo featu...

Страница 499: ...ementation generates a configuration error The attempted specification of a 32 byte burst on platforms that do not support such a transfer type will result in a configuration error dmod 0 4 Destinatio...

Страница 500: ...n count is decremented and restored to the local memory If the major iteration count is completed additional processing is performed The nbytes value 0x0000_0000 is interpreted as 0x1_0000_0000 thus s...

Страница 501: ...r count has been transferred This is an indivisible operation and cannot be stalled or halted Once the minor count is exhausted the current values of the saddr and daddr are written back into the loca...

Страница 502: ...Reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R doff 16 31 W Reset Figure 15 31 TCDn Word 5 TCDn citer doff fields Table 15 26 TCDn Word 5 TCDn doff citer field descriptions Name Description...

Страница 503: ...pleted and updated in the transfer control descriptor memory Once the major iteration count is exhausted the channel performs a number of operations e g final source and destination address calculatio...

Страница 504: ...r to be loaded into this channel This channel reload is performed as the major iteration count completes The scatter gather address must be 0 modulo 32 else a configuration error is reported Address D...

Страница 505: ...ed the contents of the entire 16 bit biter entry is reloaded into the 16 bit citer entry When the biter field is initially loaded by software it must be set to the same value as that contained in the...

Страница 506: ...he link target channel initiates a channel service request via an internal mechanism that sets the TCD start bit of the specified channel To support the dynamic linking coherency model this field is f...

Страница 507: ...or is read from the local memory and loaded into the registers of the other addr_path channel_ x y Once the inner minor loop completes execution the addr_path hardware writes the new values for the in...

Страница 508: ...the sizes are not equal multiple access of the smaller size data are required for each reference of the larger size As an example if the source size references 16 bit data and the destination is 32 bi...

Страница 509: ...ired source reads and destination writes to perform the actual data movement The source reads are initiated and the fetched data is temporarily stored in the data_path module until it is gated onto th...

Страница 510: ...ns which are performed These include the final address adjustments and reloading of the biter field into the citer Additionally assertion of an optional interrupt request occurs at this time as does a...

Страница 511: ...ominant a measure of the requests which can be serviced in a fixed time is a more interesting metric In this environment the speed of the source and destination address spaces remains important but th...

Страница 512: ...t with the registering of the IPS write to TCD word7 Cycle 3 Channel arbitration begins Cycle 4 Channel arbitration completes The transfer control descriptor local memory read is initiated Cycle 5 6 T...

Страница 513: ...the AHB system bus DMA requests can be processed every 9 cycles Assuming an average of the access times associated with IPS to SRAM 4 cycles and SRAM to IPS 5 cycles DMA requests can be processed ever...

Страница 514: ...itration pipeline and one extra cycle on the hardware request resulting from the internal registering of the ipd_req signals For the peak request rate calculations above the arbitration and request re...

Страница 515: ...fore the next activation of the problem channel the error will be detected and recorded again The sequence listed below is correct For item 2 the dma_ipd_ack done lines will assert only if the selecte...

Страница 516: ...algorithm will select the highest pending request from the next group in the round robin sequence Servicing continues round robin always servicing the highest priority channel in the next group in the...

Страница 517: ...group arbitration fixed channel arbitration but all the channels in the highest priority group will be serviced Service latency will be short on the highest priority group but can become much longer...

Страница 518: ...006 read_byte 0x1007 d write_word 0x2004 second iteration of the minor loop e read_byte 0x1008 read_byte 0x1009 read_byte 0x100a read_byte 0x100b f write_word 0x2008 third iteration of the minor loop...

Страница 519: ...read_byte 0x100e read_byte 0x100f h write_word 0x200c last iteration of the minor loop 6 DMA engine writes TCD saddr 0x1010 TCD daddr 0x2010 TCD citer 1 7 DMA engine writes TCD active 0 8 The channel...

Страница 520: ...TCD start 0 TCD active 0 TCD done 0 channel has completed the minor loop and is idle or TCD start 0 TCD active 0 TCD done 1 channel has completed the major loop and is idle The best method to test fo...

Страница 521: ...p indicates a higher priority channel is actively preempting a lower priority channel The worst case latency when switching to a preempt channel is the summation of arbitration latency 2 cycles bandwi...

Страница 522: ...to fixed arbitration mode 2 Disable all the channels within a group then change the channel priorities within that group only then enable the appropriate channels The following two options are availa...

Страница 523: ...s TCD word7 after that channel s TCD done bit is set indicating the major loop is complete NOTE The user must clear the TCD done bit before writing the TCD major e_link or TCD e_sg bits The TCD done...

Страница 524: ...Enhanced Direct Memory Access eDMA MPC5606S Microcontroller Reference Manual Rev 7 522 Freescale Semiconductor...

Страница 525: ...e ECSM includes these features Program visible information on the device configuration and revision Optional registers for capturing information on memory errors if error correcting codes ECC are impl...

Страница 526: ...ed 0x0C Reserved Misc Reset Status MRSR 0x10 Reserved Misc Wakeup Control MWCR 0x14 Reserved 0x18 Reserved 0x1C Reserved Misc Interrupt MIR 0x20 Reserved 0x24 Miscellaneous User Defined Control Regist...

Страница 527: ...IPS programming model Any attempted write is ignored See Figure 16 2 and Table 16 3 for the Revision definition 16 4 2 3 Miscellaneous Reset Status Register MRSR The MRSR contains a bit for each of th...

Страница 528: ...s is signaled to the ECSM and external logic This assertion if properly enabled by MWCR ENBWCR causes the ECSM output signal enter_low_power_mode to be set This in turn causes the selected external lo...

Страница 529: ...RILVL 0 3 W Reset 0 1 0 0 0 0 0 0 Figure 16 4 Miscellaneous Wakeup Control MWCR Register Table 16 5 Wakeup Control MWCR field descriptions Name Description 0 ENBWCR Enable WCR 0 MWCR is disabled 1 MWC...

Страница 530: ...has not occurred 1 A flash memory bank 0 stall has occurred The interrupt request is negated by writing a 1 to this bit Writing a 0 has no effect 2 FB1AI Flash Bank 1 Abort Interrupt 0 A flash memory...

Страница 531: ...Address Register REAR RAM ECC Syndrome Register RESR RAM ECC Master Number Register REMR RAM ECC Attributes Register REAT RAM ECC Data Register REDR The details on the ECC registers are provided in t...

Страница 532: ...generates an ECSM ECC interrupt request as signaled by the assertion of ESR R1BC The address attributes and data are also captured in the REAR RESR REMR REAT and REDR registers 3 EF1BR Enable Flash 1...

Страница 533: ...e ESR to be asserted at any given time This preserves the association between the ESR and the corresponding address and attribute registers which are loaded on each occurrence of a properly enabled EC...

Страница 534: ...ECC interrupt request The address attributes and data are also captured in the REAR RESR REMR REAT and REDR registers To clear this interrupt flag write a 1 to this bit Writing a 0 has no effect 3 F1...

Страница 535: ...10 ECC Error Generation EEGR field descriptions Name Description 2 FRC1BI Force RAM Continuous 1 Bit Data Inversions 0 No RAM continuous 1 bit data inversions are generated 1 1 bit data inversions in...

Страница 536: ...erall odd parity bit continuously on every write operation After this bit has been enabled to generate another continuous noncorrectable data inversion it must be cleared before being set again to pro...

Страница 537: ...the bit specified by this field plus the odd parity bit of the ECC code are inverted The RAM controller follows a vector bit ordering scheme where LSB 0 Errors in the ECC syndrome bits can be generate...

Страница 538: ...flash memory Depending on the state of the ECC Configuration Register an ECC event in the flash memory causes the address attributes and data associated with the access to be loaded into the FEAR FEMR...

Страница 539: ...3 and Table 16 14 for the Flash ECC Data Register definition Address Base 0x0057 Access User read only 0 1 2 3 4 5 6 7 R Write Size 0 2 Protection 0 3 W Reset 1 1 Value is undefined at reset Figure 16...

Страница 540: ...causes the address attributes and data associated with the access to be loaded into the REAR RESR REMR REAT and REDR registers and the appropriate flag R1BC or RNCE in the ECC Status Register to be as...

Страница 541: ...ome plus overall incorrect parity bit signal a multi bit non correctable error For correctable single bit errors the mapping shown in Table 16 16 associates the upper 7 bits of the syndrome with the d...

Страница 542: ...rly enabled ECC event in the RAM memory Depending on the state of the ECC Configuration Register an ECC event in the RAM causes the address attributes and data associated with the access to be loaded...

Страница 543: ...AM ECC Attributes REAT field descriptions Name Description 0 Write AMBA AHB HWRITE 0 AMBA AHB read access 1 AMBA AHB write access 1 3 Size 0 2 AMBA AHB HSIZE 0 2 000 8 bit AMBA AHB access 001 16 bit A...

Страница 544: ...the duration of interrupt servicing If the corresponding processor is configured to allow high priority elevation on external interrupt events the ECSM generates the high priority signal upon externa...

Страница 545: ...INTC ips_supervisor_access ips_module_en 4 0 SPP_IPS_REG_PROTECTION qual_ips_mod_en 0 ips_xfr_wait 0 ips_xfr_err 0 ECSM qual_ips_mod_en 1 ips_xfr_wait 1 ips_xfr_err 1 STM qual_ips_mod_en 3 ips_xfr_wai...

Страница 546: ...Error Correction Status Module ECSM MPC5606S Microcontroller Reference Manual Rev 7 544 Freescale Semiconductor...

Страница 547: ...emory Map for exact memory sizes of each family member Figure 17 1 MPC5606S flash memory architecture 17 2 Program flash memory code flash 0 and code flash 1 17 2 1 Introduction The primary function o...

Страница 548: ...logic A BIU connects the flash module to a system bus and contains all system level customization required for the SoC application 17 2 2 Main features High read parallelism 128 bits Error Correction...

Страница 549: ...de ECC and or error detection The ECC implemented within the flash module will correct single bit failures and detect double bit failures The flash module uses an embedded hardware algorithm implement...

Страница 550: ...17 1 Table 17 1 Flash module sectorization AP Size KB 5602S 5604S 5606S Sector Region Start Address End Address On chip Flash Memories Code Flash 0x00000000 0x00007FFF 32 Yes Yes Yes1 B0F0 Code Flash...

Страница 551: ...h Array 0 Test Sector 0x00404000 0x0047FFFF 496 Reserved 0x00480000 0x00483FFF 16 No No Yes Code Flash Array 1 Test Sector 0x00484000 0x007FFFFF 3568 Reserved On chip Flash Memories Data Flash 0x00800...

Страница 552: ...E7 232 byte NVLML Non Volatile Low Mid Address Space Block Locking Register 0xC03DE8 to 0xC03DEF 8 byte NVHBL Non Volatile High Address space Block Locking Register 0xC03DF0 to 0xC03DF7 8 byte NVSLL N...

Страница 553: ...se of the Shadow block is done similarly as a sector erase The Shadow block contains specified data needed for user features The user area of the Shadow block may be used for user defined functions po...

Страница 554: ...writes attempted to invalid locations will result in an interlock occurring but attempts to program these blocks will not occur since they are forced to be locked Erase will occur to selected and unlo...

Страница 555: ...ode If the flash memory module enters Power Down mode during an erase operation the MCR ESUS bit is set The user may resume the erase operation when the module exits Power Down mode by clearing the MC...

Страница 556: ...ace Block Locking Register LML 0x0004 on page 560 High Address Space Block Locking Register HBL 0x0008 on page 563 Secondary Low mid Address Space Block Lock Register SLL 0x000C on page 564 Low mid Ad...

Страница 557: ...lization ends setting the PEG bit of MCR to 0 In this section the following abbreviations are used 17 2 6 1 Module Configuration Register MCR The Module Configuration Register is used to enable and mo...

Страница 558: ...2 0 Read Only The value of SIZE field is dependent upon the size of the flash module according to Table 17 9 8 Reserved Read Only Write this bit has no effect and read this bit always outputs 0 9 11 L...

Страница 559: ...the main address space is active for all flash module program and erase operations PEAS 1 indicates that the test or shadow address space is active for program and erase The value in PEAS is captured...

Страница 560: ...ray Integrity Check or Margin mode PEG is set to 1 when the operation is completed regardless of the occurrence of any error The presence of errors can be detected only by comparing the checksum value...

Страница 561: ...under one of the following conditions Erase ERS 1 ESUS 0 UT0 AIE 0 Program ERS 0 ESUS 0 PGM 1 UT0 AIE 0 In normal operation a 1 to 0 transition of EHV with DONE high and ESUS low terminates the curren...

Страница 562: ...t changing priorities are detailed in the following table If the user attempts to write two or more MCR bits simultaneously then only the bit with the lowest priority level will be written 17 2 6 2 Lo...

Страница 563: ...0 0 0 TSLK 0 0 MLK1 MLK0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 rw X r 0 r 0 rw X rw X 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LLK1 5 LLK1 4 LLK1 3 LLK1 2 LLK1 1 LLK1 0 LLK9 LLK8 LLK7 LL...

Страница 564: ...0 Mid address space block LocK 1 0 Read Write These bits are used to lock the blocks of Mid Address Space from Program and Erase For Code flash 0 MLK1 0 are related to sectors B0F7 6 respectively For...

Страница 565: ...once an interlock write is completed until MCR DONE is set at the completion of the requested operation Likewise the LLK register is not writable if a high voltage operation is suspended Upon reset i...

Страница 566: ...blocks of High Address Space from Program and Erase All the HLK5 0 are not used for both Code flash 0 and 1 that are all mapped in mid and low address space A value of 1 in a bit of the HLK register s...

Страница 567: ...0 STSL K 0 0 SMK1 SMK0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 rw X r 0 r 0 rw X rw X 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SLK1 5 SLK1 4 SLK1 3 SLK1 2 SLK1 1 SLK1 0 SLK9 SLK8 SLK7 SLK6...

Страница 568: ...SMK1 0 Secondary Mid address space block locK 1 0 Read Write These bits are used as an alternate means to lock the blocks of Mid Address Space from Program and Erase For Code flash 0 SMK1 0 are relate...

Страница 569: ...t will cause the bits to go back to their Test flash block value The default value of the SLK bits assuming erased fuses would be locked In the event that blocks are not present due to configuration o...

Страница 570: ...e of 1 in the select register signifies that the block is selected for erase A value of 0 in the select register signifies that the block is not selected for erase The reset value for the select regis...

Страница 571: ...as part of the Erase sequence The select register is not writable once an interlock write is completed or if a high voltage operation is suspended In the event that blocks are not present due to conf...

Страница 572: ...mode the Address Register is read only Note An erroneous update of the Address register ADR occurs whenever there is a sequence of three or more events affecting the ADR ECC single or double bit error...

Страница 573: ...13 14 15 BI031 BI030 BI029 BI028 BI027 BI026 BI025 BI024 BI023 BI022 BI021 BI020 BI019 BI018 BI017 BI016 rw X rw X rw X rw X rw X rw X rw X rw X rw X rw X rw X rw X rw X rw X rw X rw X 16 17 18 19 20...

Страница 574: ...that contains the default reset value for BIU2 The NVBIU2 register is read during the reset phase of the flash module and loaded into the BIU2 The NVBIU2 register is a 64 bit register the 32 most sign...

Страница 575: ...egister can be locked The use of this bus is SoC specific Address Offset 0x0003C Reset value 0x00000001 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 UTE 0 0 0 0 0 0 0 DSI7 DSI6 DSI5 DSI4 DSI3 DSI2 DSI1 DSI0...

Страница 576: ...ue Read Write If MRE is high MRV selects the margin level that is being checked Margin can be checked to an erased level MRV 1 or to a programmed level MRV 0 This bit is not accessible whenever MCR DO...

Страница 577: ...ed to signify the operation is on going Once completed AID will be set to indicate that the Array Integrity Check is complete At this time the MISR UMISR0 4 can be checked 0 Array Integrity Check is o...

Страница 578: ...27 28 29 30 31 DAI47 DAI46 DAI45 DAI44 DAI43 DAI42 DAI41 DAI40 DAI39 DAI38 DAI37 DAI36 DAI35 DAI34 DAI33 DAI32 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Figure 17...

Страница 579: ...ating the bits 31 0 of all the pages read from the flash memory The MS can be seeded to any value by writing the UMISR0 register Address Offset 0x0004C Reset value 0x00000000 0 1 2 3 4 5 6 7 8 9 10 11...

Страница 580: ...5 26 27 28 29 30 31 MS07 9 MS07 8 MS07 7 MS07 6 MS07 5 MS07 4 MS07 3 MS07 2 MS07 1 MS07 0 MS06 9 MS06 8 MS06 7 MS06 6 MS06 5 MS06 4 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw...

Страница 581: ...en Double Word The UMISR4 Register is not accessible whenever MCR DONE or UT0 AID are low reading returns indeterminate data while writing has no effect Table 17 29 UMISR3 field descriptions Field Des...

Страница 582: ...ECC error detection for odd Double Word on MS154 the double ECC error detection for odd Double Word on MS155 The MS can be seeded to any value by writing the UMISR4 register Address Offset 0x203DD8 Re...

Страница 583: ...51 PWD 50 PWD 49 PWD 48 rw X rw X rw X rw X rw X rw X rw X rw X rw X rw X rw X rw X rw X rw X rw X rw X 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 PWD 47 PWD 46 PWd4 5 PWD 44 PWD 43 PWD 42 PWD 41...

Страница 584: ...s disabled If CW15 0 0x55AA or NVSCI1 NVSCI0 the Censored mode is enabled Address Offset 0x203DE4 Delivery value 0x55AA55AA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SC31 SC30 SC29 SC28 SC27 SC26 SC25 SC2...

Страница 585: ...X rw X rw X rw X rw X rw X rw X rw X rw X rw X rw X rw X rw X Figure 17 25 Non volatile User Options register NVUSRO Table 17 35 NVUSRO field descriptions Field Description 0 28 UO31 03 User Options 3...

Страница 586: ...steps The first instruction is used to select the desired operation by setting its corresponding selection bit in MCR PGM or ERS or UT0 MRE or EIE The second step is the definition of the operands th...

Страница 587: ...within the double word Programming changes the value stored in an array bit from logic 1 to logic 0 only Programming cannot change a stored logic 0 to a logic 1 Addresses in locked disabled blocks can...

Страница 588: ...ll result in MCR PEG being set low indicating a failed operation MCR DONE must be checked to know when the aborting command has completed The data space being operated on before the abort will contain...

Страница 589: ...s written during erase sequence interlock writes are ignored The user may terminate the erase sequence by clearing ERS before setting EHV An erase operation may be aborted by clearing MCR EHV assuming...

Страница 590: ...here is no need to clear MCR EHV and MCR ERS in order to perform reads during erase suspend The Erase sequence is resumed by writing a logic 0 to MCR ESUS MCR EHV must be set to 1 before MCR ESUS can...

Страница 591: ...y the MISR The MISR can be seeded to any value by writing the UMISR0 4 registers The Array Integrity Self Check consists of the following sequence of events 1 Set UTE in UT0 by writing the related pas...

Страница 592: ...pacted by the execution of Margin reads Doing Margin reads repetitively results in degradation of the flash memory array and shorten expected lifetime experienced at normal read levels For these reaso...

Страница 593: ...t AIE in UT0 Operation Start do Loop to wait for AID 1 tmp UT0 Read UT0 while tmp 0x00000001 data0 UMISR0 Read UMISR0 content data1 UMISR1 Read UMISR1 content data2 UMISR2 Read UMISR2 content data3 UM...

Страница 594: ...sage of an error correction code ECC The word size is fixed at 64 bits At each double word of 64 bits there are associated 8 ECC bits that are programmed in such a way to guarantee a Single Error Corr...

Страница 595: ...le registers can be written at 0 or 1 at any time therefore the user application can lock and unlock sectors when desired 17 2 7 3 2 Censored mode The Censored mode information is stored in non volati...

Страница 596: ...d non volatile storage elements sense amplifiers row decoders column decoders and charge pumps The arrayed storage elements in the flash core are subdivided into physically separate units referred to...

Страница 597: ...matrix module composed of a single bank Bank 0 normally used for Code storage No Read While Modify operations are possible The Modify operations are managed by an embedded Flash Program Erase Control...

Страница 598: ...rithm to guard against accidental program erase The hardware algorithm perform the steps necessary to ensure that the storage elements are programmed and erased with sufficient margin to guarantee dat...

Страница 599: ...k User mode program of the test block are enabled only when MCR PEAS is high also if the Shadow block is available The Test flash block may be locked unlocked against program by using the LML TSLK and...

Страница 600: ...enabled User mode read The read state is active when MCR ERS and MCR ESUS are high and MCR PGM is low Erase Suspend Notice that no Read While Modify is available Flash core reads return 128 bits 1 pag...

Страница 601: ...ary write access is locked on all the registers in Power Down mode When enabled the flash module returns to its previous state in all cases unless in the process of executing an erase high voltage ope...

Страница 602: ...tions of Test flash sector with a special meaning During the flash memory initialization phase the FPEC reads these non volatile registers and update their related Volatile Registers When the FPEC det...

Страница 603: ...0 0 0 SIZE 2 SIZE 1 SIZE 0 0 LAS2 LAS1 LAS0 0 0 0 MAS rc 0 r 0 r 0 r 0 r 0 r 1 r 1 r 0 r 0 r 1 r 1 r 0 r 0 r 0 r 0 r 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 EER RWE 0 0 PEAS DON E PEG 0 0 0...

Страница 604: ...rom the last reset or clearing of EER were correct Since this bit is an error flag it must be cleared to 0 by writing 1 to the register location A write of 0 will have no effect 0 Reads are occurring...

Страница 605: ...Only The PEG bit indicates the completion status of the last flash program or erase sequence for which high voltage operations were initiated The value of PEG is updated automatically during the Progr...

Страница 606: ...d PGM is low and UT0 AIE is low ERS can be cleared by the user only when ESUS and EHV are low and DONE is high ERS is cleared on reset 0 Flash is not executing an Erase sequence 1 Flash is executing a...

Страница 607: ...art a Program Erase sequence EHV may be set under one of the following conditions Erase ERS 1 ESUS 0 UT0 AIE 0 Program ERS 0 ESUS 0 PGM 1 UT0 AIE 0 In normal operation a 1 to 0 transition of EHV with...

Страница 608: ...0 0 0 TSLK 0 0 MLK1 MLK0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 rw X r 0 r 0 rw X rw X 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LLK1 5 LLK1 4 LLK1 3 LLK1 2 LLK1 1 LLK1 0 LLK9 LLK8 LLK7 LLK...

Страница 609: ...space block LocK 1 0 Read Write These bits are used to lock the blocks of Mid Address Space from Program and Erase All the MLK1 0 are not used for this memory cut that is all mapped in low address sp...

Страница 610: ...s The LLK register is not writable once an interlock write is completed until MCR DONE is set at the completion of the requested operation Likewise the LLK register is not writable if a high voltage o...

Страница 611: ...0 are not used for this memory cut that is all mapped in low address space A value of 1 in a bit of the HLK register signifies that the corresponding block is locked for Program and Erase A value of...

Страница 612: ...STSL K 0 0 SMK1 SMK0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 r 0 rw X r 0 r 0 rw X rw X 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SLK1 5 SLK1 4 SLK1 3 SLK1 2 SLK1 1 SLK1 0 SLK9 SLK8 SLK7 SLK6 S...

Страница 613: ...ary Mid address space block locK 1 0 Read Write These bits are used as an alternate means to lock the blocks of Mid Address Space from Program and Erase All the SMK1 0 are not used for this memory cut...

Страница 614: ...t will cause the bits to go back to their Test flash block value The default value of the SLK bits assuming erased fuses would be locked In the event that blocks are not present due to configuration o...

Страница 615: ...0 Low address space block SeLect 15 0 Read Write A value of 1 in the select register signifies that the block is selected for erase A value of 0 in the select register signifies that the block is not...

Страница 616: ...f the Erase sequence The select register is not writable once an interlock write is completed or if a high voltage operation is suspended In the event that blocks are not present due to configuration...

Страница 617: ...e In User mode the Address Register is read only Note An erroneous update of the Address register ADR occurs whenever there is a sequence of three or more events affecting the ADR ECC single or double...

Страница 618: ...ication when User Test is enabled All bits in UT0 2 and UMISR0 4 are locked when this bit is 0 This bit is not writeable to a 1 but may be cleared The reset value is 0 The method to set this bit is to...

Страница 619: ...ce AIS 0 is meant to replicate sequences normal user code follows and thoroughly checks the read propagation paths This sequence is proprietary The alternative sequence AIS 1 is just logically sequent...

Страница 620: ...w 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 DAI15 DAI14 DAI13 DAI12 DAI11 DAI10 DAI09 DAI08 DAI07 DAI06 DAI05 DAI04 DAI03 DAI02 DAI01 DAI00 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw...

Страница 621: ...n the double word 0 The array bit is forced at 0 1 The array bit is forced at 1 Address Offset 0x00048 Reset value 0x00000000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MS03 1 MS03 0 MS02 9 MS02 8 MS02 7 M...

Страница 622: ...04 4 MS04 3 MS04 2 MS04 1 MS04 0 MS03 9 MS03 8 MS03 7 MS03 6 MS03 5 MS03 4 MS03 3 MS03 2 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Figure 17 38 User Multiple Inpu...

Страница 623: ...MS095 064 Multiple input Signature 095 064 Read Write These bits represent the MISR value obtained accumulating the bits 95 64 of all the pages read from the flash memory The MS can be seeded to any v...

Страница 624: ...is possible on any other sector Read While Modify is not supported Address Offset 0x00058 Reset value 0x00000000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MS15 9 MS15 8 MS15 7 MS15 6 MS15 5 MS15 4 MS15 3...

Страница 625: ...t started one operation can be canceled by resetting the operation selection bit A summary of the available flash memory modify operations are shown in the following Table 17 36 In general each Modify...

Страница 626: ...ed Write the first address to be programmed with the program data The flash module latches address bits 22 3 at this time The flash module latches data written as well This write is referred to as a p...

Страница 627: ...to wait for DONE 1 tmp MCR Read MCR while tmp 0x00000400 status MCR 0x00000200 Check PEG flag MCR 0x00000010 Reset EHV in MCR Operation End MCR 0x00000000 Reset PGM in MCR Deselect Operation 17 3 7 3...

Страница 628: ...17 9 Erase of sectors B0F1 and B0F2 MCR 0x00000004 Set ERS in MCR Select Operation LMS 0x00000006 Set LSL2 1 in LMS Select Sectors to erase 0x000000 0xFFFFFFFF Latch a Flash Address with any data MCR...

Страница 629: ...eck Margin mode Read ECC Logic Check The User Test mode is equivalent to a Modify operation read accesses attempted by the user during User Test mode generates a Read While Write Error RWE of MCR set...

Страница 630: ...the Array Integrity Check 5 Wait until the UT0 AID bit goes high 6 Compare UMISR0 4 content with the expected result 7 Write a logic 0 to the UT0 AIE bit 8 If more blocks are to be checked return to s...

Страница 631: ...the appropriate register s in LMS or HBS registers Note that Lock and Select are independent If a block is selected and locked no Array Integrity Check will occur 3 Set eventually UT0 AIS bit for a s...

Страница 632: ...32 the Double Word Input value 3 Write in UT0 DSI7 0 the Syndrome Input value 4 Select the ECC Logic Check write a logic 1 to the UT0 EIE bit 5 Write a logic 1 to the UT0 AIE bit to start the ECC Logi...

Страница 633: ...oughout the life of the product with no impact to product reliability 17 3 8 1 ECC algorithm The flash memory macrocell supports one ECC algorithm All 1s No Error This algorithm detects as valid any D...

Страница 634: ...in volatile registers that act as actuators The reset state of all the volatile modify protection registers is the protected state All the non volatile modify protection registers can be programmed t...

Страница 635: ...the Test flash one time programmable that is not erasable once unlocked the sectors cannot be locked again Of course on the contrary all the volatile registers can be written at 0 or 1 at any time the...

Страница 636: ...mory Protection Unit MPU 2 port Platform Flash memory controller PFLASH2P_LCA with connections to 3 memory banks Platform RAM memory controller PRAM AHB to IPS APB bus controller PBRIDGE Lite for acce...

Страница 637: ...s Recall the maximum capacity of the low cost array is 512 KB so devices with larger flash memory bank sizes require multiple instantiations of the array Within a bank the array instantiations are nam...

Страница 638: ...structured to support simultaneous AHB accesses from the two ports fully in parallel when the references are targeted to different memory banks If simultaneous AHB accesses reference the same bank the...

Страница 639: ...cycle read responses zero AHB data phase wait states for accesses that hit in the holding register There is no support for prefetching associated with this bank Programmable response for read while wr...

Страница 640: ...l_rdata h d t bk0_fl_addr 24 Dual Port p0_hrdata p0_haddr hattr Interface p1_haddr hattr p1_hwdata config control array0_biu0_regout 31 0 array0_biu1_regout 31 0 array0_biu2_regout 31 0 array0_biu3_re...

Страница 641: ...for the flash memory space and another for the program visible control and configuration registers The flash memory space is accessed via the AMBA AHB ports while the program visible registers are acc...

Страница 642: ...r 0x0048_0000 0x004F_FFFF 512 Bank2 Code flash array 1 test sector 0x0050_0000 0x0057_FFFF 512 Bank0 Reserved for Code flash array 2 test sector 0x0058_0000 0x005F_FFFF 512 Bank2 Reserved for Code fla...

Страница 643: ...present arrays be set to the bank0 array0 values NOTE To perform program and erase operations the control registers in the actual referenced flash array must be programmed but the configuration of th...

Страница 644: ...pc b1_apc address pipeline control b02_wwsc b1_wwsc write wait state control b02_rwsc b1_rwsc read wait state control b02_rwwc b1_rwwc read while write control where b02 is used to refer to configurat...

Страница 645: ...to a value appropriate to the operating frequency of the PFLASH The required settings are documented in Table 17 70 Higher operating frequencies require non zero settings for this field for proper fl...

Страница 646: ...hardware reset enabling the stall while write erase and disabling the abort and notification interrupts B02_P1_BCFG Bank0 2 Port 1 Page Buffer Configuration This field controls the configuration of th...

Страница 647: ...are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches and buffers 2 and 3 for data accesses 11 The buffers are partitioned into two groups with buffers 0 1 2 allocated...

Страница 648: ...ettings are documented in the SoC specification Higher operating frequencies require non zero settings for this field for proper flash operation This field is set to 0b00010 by hardware reset 00000 Ac...

Страница 649: ...This 3 bit field defines the controller response to flash reads while the array is busy with a program write or erase operation 0 Terminate any attempted read while write erase with an error response...

Страница 650: ...AP M2AP M1AP M0AP W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 17 46 PFLASH Access Protection Register PFAPR Table 17 66 PFLASH Access Protection Register field descriptions Field Description ARBM A...

Страница 651: ...ences are granted access to the bank For more information see Section 17 4 4 10 Input port arbitration 17 4 4 1 Access protections The PFLASH2P_LCA provides programmable configurable access protection...

Страница 652: ...P_LCA asserts hresp 0 and negates hready_out to signal an error has occurred On the following clock cycle the PFLASH2P_LCA asserts hready_out and holds both hresp 0 and hready_out asserted until hread...

Страница 653: ...ress attributes data and ECC information see the ECSM chapter 17 4 4 8 Bank 0 and 2 page read buffers and prefetch operation The logic associated with banks 0 and 2 of the PFLASH2P_LCA contains four p...

Страница 654: ...6 Busy Fill the buffer has been allocated to receive data from the flash array and the array access is still in progress Selection of a buffer to be loaded on a miss is based on the following replacem...

Страница 655: ...and 2 are allocated for instruction fetches and buffer 3 reserved for data accesses 17 4 4 8 4 Buffer invalidation The page read buffers may be invalidated under hardware or software control Any falli...

Страница 656: ...the current access address matches the address stored in the temporary holding register can be serviced in 0 AHB wait states as the stored read data is routed from the temporary register back to the r...

Страница 657: ...ted with an AHB error response and the read is blocked in the controller and not seen by the flash array Bn_RWWC 0b111 This defines the basic stall while write capability and represents the default re...

Страница 658: ...le write and abort while write operations see Figure 17 51 and Figure 17 52 respectively 17 4 4 12 Wait State emulation Emulation of other memory array timings are supported by the PFLASH2P_LCA on rea...

Страница 659: ...of the processor accesses to the platform memories e g flash and SRAM plays a major role in the overall system performance Given the core platform pipeline structure the platform s memory controllers...

Страница 660: ...eq addr y addr y 4 addr y 12 C y C y 4 okay okay okay okay okay okay okay okay y C y C y 4 Read no buffering no prefetch APC 0 RWSC 0 PFLM 0 1 2 3 4 5 6 7 8 addr y seq addr y 8 y 4 y 8 C y 8 C y 12 y...

Страница 661: ...nonseq seq seq addr y addr y 4 addr y 12 C y C y 4 okay okay okay okay okay okay okay okay y C y Burst Read buffer miss no prefetch APC 2 RWSC 2 PFLM 0 1 2 3 4 5 6 7 8 addr y seq addr y 8 y 4 addr y 4...

Страница 662: ...enabled nonseq seq seq addr y addr y 4 addr y 12 C y C y 4 C y 8 C y 12 okay okay okay okay okay okay okay okay Y C y Burst Read buffer miss no prefetch APC 2 RWSC 2 PFLM 0 1 2 3 4 5 6 7 8 addr y seq...

Страница 663: ...r y 4 addr y 12 C y C y 4 C y 8 C y 12 okay okay okay okay okay okay okay okay y C y Burst Read buffer miss prefetch APC 2 RWSC 2 PFLM 2 1 2 3 4 5 6 7 8 addr y seq addr y 8 y 16 C y 16 seq seq addr y...

Страница 664: ...ut cycles 2 9 the AHB bus pipeline is stalled with a read to address y in the AHB data phase and a read to address y 4 in the address phase Depending on the state of the least significant bit of the B...

Страница 665: ...led with a read to address y in the AHB data phase and a read to address y 4 in the address phase Depending on the state of the least significant bit of the Bn_RWWC control field the hardware may also...

Страница 666: ...g for data generally is not recommended The flash module on this device has two ports Port 0 is always connected to the core Port 1 is connected to the other non core masters DCU and eDMA Configuring...

Страница 667: ...s are mostly sequential so prefeching can improve performance Data Prefetch Enable B0_P0_DPFE 0 Data accesses are expected to generally be random not sequential Prefetch Limit B0_P0_PFLIM 3 Prefetch o...

Страница 668: ...E PFCR1 0x1084_0101 Table 17 71 Access and protection setting recommendations1 1 Result value for recommendations in PFAPR 0x03F2 005D Parameter Parameter Symbol in register PFAPR Comments Arbitration...

Страница 669: ...Flash Memory MPC5606S Microcontroller Reference Manual Rev 7 Freescale Semiconductor 667...

Страница 670: ...Flash Memory MPC5606S Microcontroller Reference Manual Rev 7 668 Freescale Semiconductor...

Страница 671: ...described in subsequent sections Figure 18 1 FlexCAN block diagram 18 1 1 Overview The CAN protocol was primarily but not only designed to be used as a vehicle serial data bus meeting the specific req...

Страница 672: ...grammable bit rate up to 1 Mb s Content related addressing Flexible Message Buffers up to 64 of 0 to 8 bytes data length Each MB configurable as Rx or Tx all supporting standard and extended messages...

Страница 673: ...cts a message that has not been acknowledged it will flag a BIT0 error without changing the REC as if it was trying to acknowledge the message Loopback mode The module enters this mode when the LPB bi...

Страница 674: ...a FlexCAN module with 64 MB capability is shown in Table 18 2 Each individual register is identified by its complete name and the corresponding mnemonic The access type can be Supervisor S or Unrestri...

Страница 675: ...ge 687 Base 0x0014 Rx Buffer 14 Mask RX14MASK S U Yes No on page 688 Base 0x0018 Rx Buffer 15 Mask RX15MASK S U Yes No on page 688 Base 0x001C Error Counter Register ECR S U Yes Yes on page 688 Base 0...

Страница 676: ...ID Extended 0x8 Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 0xC Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Figure 18 2 Message Buffer Structure Table 18 4 Message Buffer Structure field descr...

Страница 677: ...g Counter Time Stamp This 16 bit field is a copy of the Free Running Timer captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus PRIO Local priori...

Страница 678: ...emain OVERRUN Refer to Section 18 4 5 Matching process for details about overrun behavior 0XY11 BUSY Flexcan is updating the contents of the MB The CPU must not access the MB 0010 An EMPTY buffer was...

Страница 679: ...7 Rx FIFO for more information 0 1010 1010 Transmit a data frame whenever a remote request frame with the same ID is received This MB participates simultaneously in both the matching and arbitration...

Страница 680: ...Data Byte 7 0x10 Reserved to 0xDF 0xE0 ID Table 0 0xE4 ID Table 1 0xE8 ID Table 2 0xEC ID Table 3 0xF0 ID Table 4 0xF4 ID Table 5 0xF8 ID Table 6 0xFC ID Table 7 Figure 18 3 Rx FIFO Structure 0 1 2 3...

Страница 681: ...nded or standard frames are accepted into the FIFO if they match the target ID 0 Extended frames are rejected and standard frames can be accepted 1 Extended frames can be accepted and standard frames...

Страница 682: ...s whether FlexCAN is enabled or not When disabled FlexCAN shuts down the clocks to the CAN Protocol Interface and Message Buffer Management submodules This is the only bit in MCR not affected by soft...

Страница 683: ...take some time to fully propagate its effect The SOFT_RST bit remains asserted while reset is pending and is automatically negated when reset completes Therefore software can poll this bit to know wh...

Страница 684: ...lity Configuration This bit is provided to support Backwards Compatibility with previous FlexCAN versions When this bit is negated the following configuration is applied For MCUs supporting individual...

Страница 685: ...l take part in the matching and arbitration processes The reset value 0x0F is equivalent to 16 MB configuration This field should be changed only while the module is in Freeze mode Maximum MBs in use...

Страница 686: ...Segment 2 PSEG2 1 x Time Quanta 16 BOFF_MSK Bus Off Mask This bit provides a mask for the Bus Off Interrupt 0 Bus Off interrupt disabled 1 Bus Off interrupt enabled 17 ERR_MSK Error Mask This bit pro...

Страница 687: ...ecovering from Bus Off state occurs according to the CAN Specification 2 0B If the bit is asserted automatic recovering from Bus Off is disabled and the module remains in Bus Off state until the bit i...

Страница 688: ...will take some time to be actually written to the register If desired software can poll the register to discover when the data was actually written 28 LOM Listen Only Mode This bit configures FlexCAN...

Страница 689: ...ID word corresponding to message ID bits 0 28 RXIDA bits 2 30 of ID Table corresponding to message ID bits 0 28 Note that for the mask bits one to one correspondence occurs with the filter bits not w...

Страница 690: ...odule operation When the BCC bit is negated RX15MASK is used as acceptance mask for the Identifier in Message Buffer 15 When the FEN bit in MCR is set FIFO enabled the RXG14MASK also applies to elemen...

Страница 691: ...s then reset to zero If FlexCAN is in the Bus Off state then Tx_Err_Counter is cascaded together with another internal counter to count the 128th occurrences of 11 consecutive recessive bits on the bu...

Страница 692: ...C_ERR FRM_ERR STF_ERR TX_WRN RX_WRN IDLE TXRX FLT_CONF 0 BOFF_INT ERR_ INT WAK_INT W w1c w1c w1c Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18 10 Error and Status Register ESR Table 18 12 Error and...

Страница 693: ...dundancy Check Error This bit indicates that a CRC Error has been detected by the receiver node that is the calculated CRC is different from the received 0 No such occurrence 1 A CRC error occurred si...

Страница 694: ...trol Register is asserted the FLT_CONF field will indicate the Error Passive state Since the Control Register is not affected by soft reset the FLT_CONF field will not be affected by soft reset if the...

Страница 695: ...M BUF 33M BUF 32M W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 18 11 Interrupt Mask Register High IMRH Table 18 14 IMRH field descriptions Field Description BUF63M BUF32M Buffer MBi Mask Each bit en...

Страница 696: ...is set for an MB configured as Tx the writing access done by the CPU into the corresponding MB will be blocked Table 18 15 IMRL field descriptions Field Description BUF31M BUF0M BUF31M BUF0M Buffer M...

Страница 697: ...has successfully completed transmission or reception BUF7I Buffer MB7 Interrupt or FIFO Overflow If the FIFO is not enabled this bit flags the interrupt for MB7 If the FIFO is enabled this flag indica...

Страница 698: ...write operation to these registers results in an access error Address See Table 18 19 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R MI31 MI30 MI29 MI28 MI27 MI26 MI25 MI24 MI23 MI22 M...

Страница 699: ...mission an arbitration algorithm decides the prioritization of MBs to be transmitted based on the message ID optionally augmented by three local priority bits or the MB ordering Before proceeding with...

Страница 700: ...see Table 18 5 and Table 18 6 in Section 18 3 2 Message Buffer structure When the Abort feature is enabled AEN in MCR is asserted after the Interrupt Flag is asserted for a MB configured as transmit b...

Страница 701: ...ceive process To be able to receive CAN frames in the mailbox MBs the CPU must prepare one or more Message Buffers for reception by executing the following steps 1 If the MB has a pending transmission...

Страница 702: ...Status word to force an EMPTY code after reading the MB the MB is actually deactivated from any currently ongoing matching process As a result a newly received frame matching the ID of that MB may be...

Страница 703: ...ng messages with that ID Let us say that these MBs are the second and the fifth in the array When the first message arrives the matching algorithm will find the first match in MB number 2 The code of...

Страница 704: ...ut the abort request is captured and kept pending until one of the following conditions is satisfied The module loses the bus arbitration There is an error during the transmission The module is put in...

Страница 705: ...then this MB is marked as invalid to receive the frame and FlexCAN will keep looking for another matching MB within the ones it has not scanned yet If it cannot find one then the message will be lost...

Страница 706: ...Control and Status word does not lock the MB Deactivation takes precedence over locking If the CPU deactivates a locked Rx MB then its lock status is negated and the MB is marked as invalid for the c...

Страница 707: ...0 to 5 are affected by RXGMASK 18 4 8 CAN protocol related features 18 4 8 1 Remote frames A remote frame is a special kind of frame The user can program an MB to be a Request Remote frame type by wr...

Страница 708: ...4 2 Control Register CTRL 18 4 8 4 Protocol timing Figure 18 16 shows the structure of the clock generation circuitry that feeds the CAN Protocol Interface CPI submodule The clock source bit CLK_SRC...

Страница 709: ...gure 18 17 and Table 18 20 SYNC_SEG This segment has a fixed length of one time quantum Signal edges are expected to happen within this section Time Segment 1 This segment includes the Propagation Seg...

Страница 710: ...ansmit mode transfers a new value to the CAN bus at this point Sample Point A node samples the bus at this point If the three samples per bit option is selected then this point marks the position of t...

Страница 711: ...scillator clock frequency that is the PLL cannot be programmed to divide down the oscillator clock There must be a minimum ratio between the peripheral clock frequency and the CAN bit rate as specifie...

Страница 712: ...xecuting any other action otherwise the FlexCAN may operate in an unpredictable way In Freeze mode all memory mapped registers are accessible Exiting Freeze mode is done in one of the following ways C...

Страница 713: ...be guaranteed that the CPU only clears the bit causing the current interrupt For this reason bit manipulation instructions BSET must not be used to clear interrupt flags These instructions may cause a...

Страница 714: ...for initializing the FlexCAN module 18 5 1 FlexCAN initialization sequence The FlexCAN module may be reset in three ways MCU level hard reset which resets all memory mapped registers asynchronously M...

Страница 715: ...O was enabled the 8 entry ID table must be initialized Other entries in each Message Buffer should be initialized as required Initialize the Rx Individual Mask Registers Set required interrupt mask bi...

Страница 716: ...FlexCAN MPC5606S Microcontroller Reference Manual Rev 7 714 Freescale Semiconductor...

Страница 717: ...lock diagram Figure 19 1 is a block diagram of the JTAG Controller JTAGC Figure 19 1 JTAG controller block diagram 19 3 Overview The JTAGC provides the means to test chip functionality and connectivit...

Страница 718: ...ate machine transitions controlled by TMS Asserting power on reset results in asynchronous entry into the reset state While in reset the following actions occur The TAP controller is forced into the T...

Страница 719: ...uctions required to grant ownership of the TAP to the auxiliary TAP controllers are ACCESS_AUX_TAP_NPC ACCESS_AUX_TAP_ONCE and ACCESS_AUX_TAP_TCU Instruction opcodes for each instruction are shown in...

Страница 720: ...by so an external pullup or pulldown may be required for correct operation when debugging Standby NOTE The JTAG Clock TCK typically operates at a frequency well below the system clock frequency as spe...

Страница 721: ...2 Bypass register The bypass register is a single bit shift register path selected for serial data transfer between TDI and TDO when the BYPASS or the reserve instructions are active After entry into...

Страница 722: ...2 IEEE 1149 1 2001 JTAG Test Access Port The JTAGC uses the IEEE 1149 1 2001 TAP for accessing registers This port can be shared with other TAP controllers on the MCU For more detail on TAP sharing vi...

Страница 723: ...ate machine that interprets the sequence of logical values on the TMS pin Figure 19 5 shows the machine s states The value shown next to each state is the value of the TMS signal sampled on the rising...

Страница 724: ...achine Test logic reset Run test idle Select DR scan Select IR scan Capture DR Capture IR Shift DR Shift IR Exit1 DR Exit1 IR Pause DR Pause IR Exit2 DR Exit2 IR Update DR Update IR 1 0 1 1 1 0 0 0 0...

Страница 725: ...implements the IEEE 1149 1 2001 defined instructions listed in Table 19 3 Table 19 4 shows the implementation for silicon cut1 By mistake the Access to Nexus Port Controller is not using the standard...

Страница 726: ...ndary scan register as the shift path between TDI and TDO It allows testing of off chip circuitry and board level interconnections by driving preloaded data contained in the boundary scan register ont...

Страница 727: ...and just before the boundary scan register cells at the output pins This sampling occurs on the rising edge of TCK in the capture DR state when the SAMPLE PRELOAD instruction is active The sampled dat...

Страница 728: ...he e200z0 OnCE block Figure 19 6 e200z0 OnCE block diagram 19 9 2 e200z0 OnCE controller functional description The functional description for the e200z0 OnCE controller is the same as for the JTAGC w...

Страница 729: ...accessed in the DR scan sequence of the TAP controller and as such the Update DR state must be transitioned through in order for an access to occur In addition the Update DR state must also be transi...

Страница 730: ...nce is required 1 Place the JTAGC in reset through TAP controller state machine transitions controlled by TMS 2 Load the appropriate instruction for the test or action to be performed 010 0111 Data Va...

Страница 731: ...t s with maximum bus loading and timing The device is capable of operating at higher baud rates up to a maximum of module clock 20 with reduced bus loading The maximum communication length and the num...

Страница 732: ...dule This state can only be entered when there are no active transfers on the bus 20 3 External signal description 20 3 1 Overview The Inter Integrated Circuit I2C module has 2 external pins 20 3 2 De...

Страница 733: ...is illegal 20 4 3 Register description This section consists of register descriptions in address order Each description includes a standard register diagram with an associated figure number Details o...

Страница 734: ...cific slave address to be used by the I2 C Bus module Note The default mode of I2C Bus is Slave mode for an address match on the bus Offset 0x0001 Access User read write 0 1 2 3 4 5 6 7 R IBC W Reset...

Страница 735: ...20 5 The SCL Tap is used to generate the SCL period and the SDA Tap is used to determine the delay from the falling edge of SCL to the change of state of SDA that is the SDA hold time Table 20 5 I Bu...

Страница 736: ...A hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in Table 20 7 The equation used to generate the SDA Hold value from the IBFD bits is SDA Hold MUL scl2tap SDA_Tap 1...

Страница 737: ...4 21 46 53 17 128 21 58 65 18 80 9 38 41 19 96 9 46 49 1A 112 17 54 57 1B 128 17 62 65 1C 144 25 70 73 1D 160 25 78 81 1E 192 33 94 97 1F 240 33 118 121 20 160 17 78 81 21 192 17 94 97 22 224 33 110 1...

Страница 738: ...0 50 156 162 5E 384 66 188 194 5F 480 66 236 242 60 320 28 156 162 61 384 28 188 194 62 448 32 220 226 63 512 32 252 258 64 576 36 284 290 65 640 36 316 322 66 768 40 380 386 67 960 40 476 482 68 640...

Страница 739: ...768 132 376 388 9F 960 132 472 484 A0 640 68 312 324 A1 768 68 376 388 A2 896 132 440 452 A3 1024 132 504 516 A4 1152 196 568 580 A5 1280 196 632 644 A6 1536 260 760 772 A7 1920 260 952 964 A8 1280 1...

Страница 740: ...lear any currently pending interrupt condition 1 Interrupts from the I2 C Bus module are enabled An I2 C Bus interrupt occurs provided the IBIF bit in the status register is also set MS SL Master Slav...

Страница 741: ...he DMA TX RX request signals 1 Enable the DMA TX RX request signals Offset 0x0003 Access Read only any time1 1 With the exception of IBIF and IBAL which are software clearable 0 1 2 3 4 5 6 7 R TCF IA...

Страница 742: ...has no effect SRW Slave Read Write When IAAS is set this bit indicates the value of the R W command bit of the calling address sent from the master This bit is only valid when the I Bus is in Slave m...

Страница 743: ...2C Bus system uses a Serial Data line SDA and a Serial Clock Line SCL for data transfer All devices connected to it must have open drain or open collector outputs A logical AND function is exercised o...

Страница 744: ...denotes the beginning of a new data transfer each data transfer may contain several bytes of data and brings all slaves out of their idle states Figure 20 11 Start and stop conditions SCL SDA Start S...

Страница 745: ...s that come after an address cycle are referred to as data transfers even if they carry sub address information for the slave device Each data byte is 8 bits long Data may be changed only while SCL is...

Страница 746: ...e and stop driving the SDA output In this case the transition from master to Slave mode does not generate a stop condition Meanwhile a status bit is set by hardware to indicate loss of arbitration 20...

Страница 747: ...errupt vector 20 5 3 2 Interrupt Description There are five types of internal interrupts in the I2 C The interrupt service routine can determine the interrupt type by reading the Status Register I2 C...

Страница 748: ...data register comprises the slave calling address and the LSB which is set to indicate the direction of transfer required from the slave The bus free time i e the time between a stop condition and the...

Страница 749: ...ollowing is an example software sequence for master transmitter in the interrupt routine clear bit 1 IBSR Clear the IBIF flag if bit 5 IBCR 0 slave_mode run Slave mode routine if bit 4 IBCR 0 receive_...

Страница 750: ...ve receive mode The slave will drive SCL low in between byte transfers SCL is released when the IBDR is accessed in the required mode In slave transmitter routine the received acknowledge bit RXAK mus...

Страница 751: ...witch To Rx Mode Dummy Read From IBDR Generate Stop Signal Read Data From IBDR And Store Set TXAK 1 Generate Stop Signal 2nd Last Byte To Be Read Last Byte To Be Read Arbitration Lost Clear IBAL IAAS...

Страница 752: ...r must only transfer one byte of data per Tx Rx request This is because there is no FIFO on the I2 C block The CPU should also keep the I2 C interrupt enabled during a DMA transfer to detect the arbit...

Страница 753: ...ity ceiling protocol for coherent accesses By providing a modifiable priority mask the priority can be raised temporarily so that all tasks which share the resource cannot preempt each other Multiple...

Страница 754: ...FlexCAN 0 CAN0 9 FlexCAN 1 CAN1 9 DSPI 0 5 DSPI 1 5 LINFlex 0 3 LINFlex 1 3 Inter IC Bus Interface Controller 0 I2C0 1 Inter IC Bus Interface Controller 1 I2C1 1 Inter IC Bus Interface Controller 2 I2...

Страница 755: ...lable Hardware Vector Enable Software Set Clear Interrupt Registers Flag Bits Priority Select Registers Peripheral Interrupt Requests Module Configuration Register Highest Priority 4 Priority Comparat...

Страница 756: ...ses hardware vector mode for a given processor when the associated HVEN bit in the INTC_MCR is asserted The hardware vector enable signal to the associated processor is driven as asserted When the int...

Страница 757: ...cessing the four bytes of a register with a single access is supported provided that the access does not Table 21 2 INTC memory map Offset from INTC_BASE_ ADDR1 1 INTC_BASE_ADDR 0xFFF4_8000 Register A...

Страница 758: ...ad write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 VTES 0 0...

Страница 759: ...rting the PCP Refer to Section 21 7 5 Priority Ceiling Protocol NOTE A store to modify the PRI field that closely precedes or follows an access to a shared resource can result in a non coherent access...

Страница 760: ...bit Bit 29 is read as a 0 VTBA is narrowed to 20 bits in width Figure 21 4 INTC Interrupt Acknowledge Register INTC_IACKR Table 21 6 INTC_IACKR field descriptions Field Description 0 20 or 0 19 VTBA V...

Страница 761: ...2 Hardware vector mode The values and size of data written to the INTC_EOIR are ignored The values and sizes written to this register neither update the INTC_EOIR contents or affect whether the LIFO p...

Страница 762: ...ETx and CLRx bits CLRx will be asserted regardless of whether CLRx was asserted before the write Offset 0x0024 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 CLR4 0 0 0 0...

Страница 763: ...10 11 12 13 14 15 R 0 0 0 0 PRI204 0 0 0 0 PRI205 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 PRI206 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0...

Страница 764: ...144_147 0x00D0 INTC_PSR44_47 0x006C INTC_PSR148_151 0x00D4 INTC_PSR48_51 0x0070 INTC_PSR152_155 0x00D8 INTC_PSR52_55 0x0074 INTC_PSR156_159 0x00DC INTC_PSR56_59 0x0078 INTC_PSR160_163 0x00E0 INTC_PSR6...

Страница 765: ...be updated with the corresponding PRIn value in INTC_PSRn Furthermore clearing the peripheral interrupt request s enable bit in the peripheral or alternatively setting its mask bit has the same conse...

Страница 766: ...0x0824 4 X Platform Flash Bank 0 Abort Platform Flash Bank 0 Stall Platform Flash Bank 1 Abort Platform Flash Bank 1 Stall Platform Flash Bank 2 Abort Platform Flash Bank 2 Stall Platform Flash Bank 3...

Страница 767: ...atch on channel 2 STM 33 0x0884 4 X Match on channel 3 STM 34 0x0888 4 Reserved 35 0x088C 4 X ECC_DBD_PlatformFlash ECC_DBD_PlatformRAM ECSM 36 0x0890 4 X ECC_SBC_PlatformFlash ECC_SBC_PlatformRAM ECS...

Страница 768: ...e event interrupt ipi_int MC_RGM 57 0x08E4 4 X FXOSC counter expired ipi_int_osc FXOSC 58 0x08E8 4 O Reserved 59 0x08EC 4 X PITimer Channel 0 Periodic Interrupt Timer PIT 60 0x08F0 4 X PITimer Channel...

Страница 769: ...0 77 0x0934 4 X DSPI_SR TCF DSPI 0 78 0x0938 4 X DSPI_SR RFDF DSPI 0 79 0x093C 4 X LINFlex_RXI LINFlex 0 80 0x0940 4 X LINFlex_TXI LINFlex 0 81 0x0944 4 X LINFlex_ERR LINFlex 0 82 0x0948 4 O Reserved...

Страница 770: ...098C 4 X LINFlex_RXI LINFlex 1 100 0x0990 4 X LINFlex_TXI LINFlex 1 101 0x0994 4 X LINFlex_ERR LINFlex 1 102 0x0998 4 O Reserved 103 0x099C 4 O Reserved 104 0x09A0 4 O Reserved 105 0x09A4 4 O Reserved...

Страница 771: ...nterface Controller 1 I2C1 127 0x09FC 4 X PITimer Channel 3 Periodic Interrupt Timer PIT 128 0x0A00 4 O Reserved 129 0x0A04 4 O Reserved 130 0x0A08 4 O Reserved 131 0x0A0C 4 O Reserved 132 0x0A10 4 O...

Страница 772: ...lar I O Subsystem 0 eMIOS0 148 0x0A50 4 X EMIOS_GFR F22 F23 Enhanced Modular I O Subsystem 0 eMIOS0 149 0x0A54 4 O Reserved 150 0x0A58 4 O Reserved 151 0x0A5C 4 O Reserved 152 0x0A60 4 O Reserved 153...

Страница 773: ...O Reserved 173 0x0AB4 4 X IBIF Inter IC bus interface Controller 2 I2C2 174 0x0AB8 4 X IBIF Inter IC Bus Interface Controller 3 I2C3 175 0x0ABC 4 O Reserved 176 0x0AC0 4 O Reserved 177 0x0AC4 4 O Rese...

Страница 774: ...OVIF Stepper Stall Detect 0 SSD0 194 0x0B08 4 X BLNIF ITGIF and ACOVIF Stepper Stall Detect 1 SSD1 195 0x0B0C 4 X BLNIF ITGIF and ACOVIF Stepper Stall Detect 2 SSD2 196 0x0B10 4 X BLNIF ITGIF and ACOV...

Страница 775: ...eripheral interrupt requests The peripheral interrupt request input ports at the boundary of the INTC block are assigned specific hardwired vectors within the INTC see Table 21 1 21 6 2 Priority manag...

Страница 776: ...ty which will be written to PRI in INTC_CPR when the interrupt request to the processor is acknowledged Interrupt requests whose PRIn in INTC_PSRn are zero will not cause a preemption because their PR...

Страница 777: ...d of interrupt exception handler Before the interrupt exception handling completes INTC end of interrupt register INTC_EOIR must be written When written the associated LIFO is popped so the preempted...

Страница 778: ...pdated with the preempting peripheral or software settable interrupt request s vector when the interrupt request to the processor is asserted The INTVEC field retains that value until the next time th...

Страница 779: ...e negated An initialization sequence for allowing the peripheral and software settable interrupt requests to cause an interrupt request to the processor is interrupt_request_initialization interrupt_r...

Страница 780: ...quest mbar ensure store to clear flag bit has completed lis r3 INTC_EOIR ha form adjusted upper half of INTC_EOIR address li r4 0x0 form 0 to write to INTC_EOIR wrteei 0 disable processor recognition...

Страница 781: ...The RTOS and all of the tasks under its control typically execute with PRI in INTC current priority register INTC_CPR having a value of 0 The RTOS will execute the tasks according to whatever priority...

Страница 782: ...tion of both ISRs with different priorities and the same priority Table 21 11 Order of ISR execution example Step Step description Code executing at end of step PRI in INTC_CPR at end of step RTOS ISR...

Страница 783: ...ring Coherency A scenario can cause non coherent accesses to the shared resource For example ISR1 and ISR2 are both running on the same core and both share a resource ISR1 has a lower priority than IS...

Страница 784: ...y can be used to schedule a lower priority portion of an ISR and they may also be used by processors to interrupt other processors in a multiple processor system 21 7 7 1 Scheduling a lower priority p...

Страница 785: ...ck of data 21 7 8 Lowering priority within an ISR A common method for avoiding preemptive scheduling inefficiencies with an ISR whose work spans multiple priorities see Section 21 7 7 1 Scheduling a l...

Страница 786: ...ag bit that caused the present ISR to be executed see Section 21 6 3 1 2 End of interrupt exception handler A flag bit whose enable bit or mask bit negates its peripheral interrupt request can be clea...

Страница 787: ...Settings during Standby mode To keep the LCD driver shut down in Standby mode the following settings are needed LCDCR LCDRST 0 LCDCR LCDRCS 0 To keep the LCD driver on functioning in Standby mode the...

Страница 788: ...kplane pins can be multiplexed with other Port functions The LCD driver system consists of five major submodules Timing and control consists of registers and control logic for frame clock generation b...

Страница 789: ...ck generator Programmable bias voltage level selector Programmable output current Selectable output current boost during transitions Selectable LCD frame frequency interrupt event On chip generation o...

Страница 790: ...Table 22 3 Signal properties Name Port Function Reset Pullu p m Backplane Waveforms BP m 1 0 Backplane waveform signals that connect directly to the pads high impedance n Frontplane Waveforms FP n 1...

Страница 791: ...00 on page 798 0x28 LCDRAM Location 2 R W 0x0000_0000 on page 799 0x2C LCDRAM Location 3 R W 0x0000_0000 on page 800 0x30 LCDRAM Location 4 R W 0x0000_0000 on page 801 0x34 LCDRAM Location 5 R W 0x000...

Страница 792: ...DUTY BIAS VLCDS W Reset 0 0 0 0 0 0 0 0 8 9 10 11 12 13 14 15 R PWR BSTEN BSTSEL BSTAO LCDOCS LCDINT EOF W Reset 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 R NOF W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 2...

Страница 793: ...ts the bias voltage levels during various LCD operating modes as shown in Table 22 29 7 VLCDS LCD voltage reference select The VCLDS bit selects which supply is be used as LCD waveform reference suppl...

Страница 794: ...been executed while LCDEN is set This flag can only be cleared by writing a 1 Writing a 0 has no effect If enabled LCDINT 1 EOF causes an interrupt request 0 Defined via NOF bits frames have not been...

Страница 795: ...Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Figure 22 3 LCD Prescaler Control Register LCDPCR Table 22 7 LCDPCR field descriptions Field Description 4 7 LC...

Страница 796: ...0 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Figure 22 4 LCD Contrast Control Register LCDCCR Table 22 8 LCDCCR field descriptions Field Description 0 CCEN CCEN LCD Contrast Con...

Страница 797: ...2 23 R FP15EN FP14EN FP13EN FP12EN FP11EN FP10EN FP9EN FP8EN W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R FP7EN FP6EN FP5EN FP4EN FP3EN FP2EN FP1EN FP0EN W Reset 0 0 0 0 0 0 0 0 Figure 22 5 LCD F...

Страница 798: ...P41EN FP40EN W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R FP39EN FP38EN FP37EN FP36EN FP35EN FP34EN FP33EN FP32EN W Reset 0 0 0 0 0 0 0 0 Figure 22 6 LCD Frontplane Enable Register 1 FPENR1 Table...

Страница 799: ...P3 FP1BP2 FP1BP1 FP1BP0 W Reset 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 R 0 0 FP2BP5 FP2BP4 FP2BP3 FP2BP2 FP2BP1 FP2BP0 W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R 0 0 FP3BP5 FP3BP4 FP3BP3 FP3BP...

Страница 800: ...P3 FP5BP2 FP5BP1 FP5BP0 W Reset 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 R 0 0 FP6BP5 FP6BP4 FP6BP3 FP6BP2 FP6BP1 FP6BP0 W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R 0 0 FP7BP5 FP7BP4 FP7BP3 FP7BP...

Страница 801: ...P2 FP9BP1 FP9BP0 W Reset 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 R 0 0 FP10BP5 FP10BP4 FP10BP3 FP10BP2 FP10BP1 FP10BP0 W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R 0 0 FP11BP5 FP11BP4 FP11BP3 FP1...

Страница 802: ...3BP2 FP13BP1 FP13BP0 W Reset 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 R 0 0 FP14BP5 FP14BP4 FP14BP3 FP14BP2 FP14BP1 FP14BP0 W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R 0 0 FP15BP5 FP15BP4 FP15BP3...

Страница 803: ...7BP2 FP17BP1 FP17BP0 W Reset 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 R 0 0 FP18BP5 FP18BP4 FP18BP3 FP18BP2 FP18BP1 FP18BP0 W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R 0 0 FP19BP5 FP19BP4 FP19BP3...

Страница 804: ...1BP2 FP21BP1 FP21BP0 W Reset 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 R 0 0 FP22BP5 FP22BP4 FP22BP3 FP22BP2 FP22BP1 FP22BP0 W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R 0 0 FP23BP5 FP23BP4 FP23BP3...

Страница 805: ...5BP2 FP25BP1 FP25BP0 W Reset 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 R 0 0 FP26BP5 FP26BP4 FP26BP3 FP26BP2 FP26BP1 FP26BP0 W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R 0 0 FP27BP5 FP27BP4 FP27BP3...

Страница 806: ...9BP2 FP29BP1 FP29BP0 W Reset 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 R 0 0 FP30BP5 FP30BP4 FP30BP3 FP30BP2 FP30BP1 FP30BP0 W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R 0 0 FP31BP5 FP31BP4 FP31BP3...

Страница 807: ...3BP2 FP33BP1 FP33BP0 W Reset 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 R 0 0 FP34BP5 FP34BP4 FP34BP3 FP34BP2 FP34BP1 FP34BP0 W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R 0 0 FP35BP5 FP35BP4 FP35BP3...

Страница 808: ...7BP2 FP37BP1 FP37BP0 W Reset 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 R 0 0 FP38BP5 FP38BP4 FP38BP3 FP38BP2 FP38BP1 FP38BP0 W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R 0 0 FP39BP5 FP39BP4 FP39BP3...

Страница 809: ...1BP2 FP41BP1 FP41BP0 W Reset 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 R 0 0 FP42BP5 FP42BP4 FP42BP3 FP42BP2 FP42BP1 FP42BP0 W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R 0 0 FP43BP5 FP43BP4 FP43BP3...

Страница 810: ...5BP2 FP45BP1 FP45BP0 W Reset 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 R 0 0 FP46BP5 FP46BP4 FP46BP3 FP46BP2 FP46BP1 FP46BP0 W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R 0 0 FP47BP5 FP47BP4 FP47BP3...

Страница 811: ...9BP2 FP49BP1 FP49BP0 W Reset 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 R 0 0 FP50BP5 FP50BP4 FP50BP3 FP50BP2 FP50BP1 FP50BP0 W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R 0 0 FP51BP5 FP51BP4 FP51BP3...

Страница 812: ...3BP2 FP53BP1 FP53BP0 W Reset 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 R 0 0 FP54BP5 FP54BP4 FP54BP3 FP54BP2 FP54BP1 FP54BP0 W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R 0 0 FP55BP5 FP55BP4 FP55BP3...

Страница 813: ...7BP2 FP57BP1 FP57BP0 W Reset 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 R 0 0 FP58BP5 FP58BP4 FP58BP3 FP58BP2 FP58BP1 FP58BP0 W Reset 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 R 0 0 FP59BP5 FP59BP4 FP59BP3...

Страница 814: ...Address Base 0x5C Access User read write 0 1 2 3 4 5 6 7 R 0 0 FP60BP5 FP60BP4 FP60BP3 FP60BP2 FP60BP1 FP60BP0 W Reset 0 0 0 0 0 0 0 0 8 9 10 11 12 13 14 15 R 0 0 FP61BP5 FP61BP4 FP61BP3 FP61BP2 FP61...

Страница 815: ...divider is set by the LCD Clock Prescaler bits in the LCD Prescaler Control Register according to Table 22 27 The following formula may be used to calculate the LCD frame frequency Eqn 22 1 Example C...

Страница 816: ...will contribute towards lowering the VONRMS and VOFFRMS voltages over the segment For this reason the whole frame is divided into steps The value from the Contrast Control register LCC determines how...

Страница 817: ...with the internal address and data buses of the MCU It is possible to read from LCD RAM locations for scrolling purposes Writing or reading of the LCDEN bit does not change the contents of the LCD RAM...

Страница 818: ...apping Frontplanes FP 39 0 and BP 3 0 will stay the same because condition n 44 is not fulfilled 22 5 7 LCD bias and modes of operation The LCD64F6B driver has seven modes of operation 1 1 Duty 1 back...

Страница 819: ...eforms generated are dependent on the state ON or OFF of the LCD segments as defined in the LCD RAM The LCD driver hardware uses the data in the LCD RAM to construct the frontplane waveform to create...

Страница 820: ...bled before entering Standby mode If the LCD64F6B is not powered down by the system and is requested to enter Standby mode and LCDRST is cleared while LCDEN is set the LCD waveform generation clocks a...

Страница 821: ...f BSTEN is set 22 5 9 3 Standard drive selection The output current has a direct impact on the power consumption and drive capability of the LCD64F6B module The PWR bits select the output current heig...

Страница 822: ...o NOF The counter is reset to request interrupt at the end of every frame as if NOF would be 0x00 if LCDEN is asserted while the LCD is off The EOF flag can only be cleared by writing a 1 Writing a 0...

Страница 823: ...D waveform examples The following figures show the timing examples of the LCD output waveforms for the available modes of operation The contrast control is disabled in all examples CCEN 0 in LCDCCR Se...

Страница 824: ...and 1 2 Bias 22 6 3 1 2 duty multiplexed with 1 3 Bias mode Duty 1 2 DUTY 001 Bias 1 3 BIAS 1 V0 VSSX V1 VLCD 1 3 V2 VLCD 2 3 V3 VLCD Only BP0 and BP1 are used a maximum of 128 segments are displayed...

Страница 825: ...0 VLCD VSSX BP0 VLCD VLCD BP0 FPx OFF 1 Frame VLCD 2 3 VLCD 2 3 VLCD 2 3 VLCD VSSX BP1 VLCD 2 3 VLCD VSSX FPx xx10 VLCD 2 3 VLCD VSSX FPy xx00 VLCD 2 3 VLCD VSSX FPz xx11 VLCD 2 3 VLCD 1 3 VLCD 1 3 0...

Страница 826: ...1 4 Duty multiplexed with 1 3 Bias mode Duty 1 4 DUTY 011 Bias 1 3 BIAS 0 or BIAS 1 V0 VSSX V1 VLCD 1 3 V2 VLCD 2 3 V3 VLCD BP4 and BP5 are not used a maximum of 256 segments are displayed 0 VLCD VSSX...

Страница 827: ...AS 0 or BIAS 1 V0 VSSX V1 VLCD 1 3 V2 VLCD 2 3 V3 VLCD BP5 is not used a maximum of 320 segments are displayed 0 VLCD VSSX BP0 VLCD VLCD BP0 FPx ON 1 Frame VLCD 2 3 VLCD 2 3 VLCD 2 3 VLCD VSSX BP1 VLC...

Страница 828: ...VSSX V1 VLCD 1 3 V2 VLCD 2 3 V3 VLCD All backplanes are used a maximum of 384 segments are displayed BP0 BP0 FPx ON 1 Frame BP1 BP2 BP1 FPx OFF FPx 10010 BP3 BP4 0 VLCD VSSX VLCD VLCD VLCD 2 3 VLCD 2...

Страница 829: ...ng The initial values of all registers are the reset values BP0 BP5 FPx ON 1 Frame BP1 BP2 BP1 FPx OFF FPx 000101 BP3 BP4 0 VLCD VSSX VLCD VLCD VLCD 2 3 VLCD 2 3 VLCD 2 3 VLCD VSSX VLCD 2 3 VLCD VSSX...

Страница 830: ...nual Rev 7 828 Freescale Semiconductor Figure 22 32 Example initialization diagram i e pulls Init Set LCDPCR Set FPENR0 1 Disable all other functions on the ports which will be used for vlcd LCDEN 1 A...

Страница 831: ...ain features 23 2 1 LIN mode features Supports LIN protocol versions 1 3 2 0 2 1 and J2602 Master mode with autonomous message handling Classic and enhanced checksum calculation and check Single 8 byt...

Страница 832: ...U load in Master mode LINFlex handles the LIN messages autonomously In Master mode once the software has triggered the header transmission LINFlex does not request any software intervention until the...

Страница 833: ...e same value as programmed in the Mantissa LINIBRR and Fraction LINFBRR registers LIN master node LIN slave node 1 LIN slave node n LIN LIN LIN Rx Tx LIN Transceiver LINFlex Controller MCU LIN Bus App...

Страница 834: ...antissa 25 620d 25d 0x19 NOTE The baud counters are updated with the new value of the baud registers after a write to LINIBRR Hence the baud register value must not be changed during a transaction The...

Страница 835: ...e sets the INIT bit in the LINCR1 To exit Initialization mode the software clears the INIT bit While in Initialization mode all message transfers to and from the LIN bus are stopped and the status of...

Страница 836: ...e LBKM and SFTM bits in the LINCR1 These bits must be configured while LINFlex is in Initialization mode Once one of the two test modes has been selected LINFlex must be started in Normal mode 23 6 1...

Страница 837: ...s register LINESR R W 0x0000_0000 on page 845 0x0010 UART mode control register UARTCR R W 0x0000_0000 on page 846 0x0014 UART mode status register UARTSR R W 0x0000_0000 on page 848 0x0018 LIN timeou...

Страница 838: ...rol register 5 IFCR5 6 R W 0x0000_0000 on page 862 0x0064 Identifier filter control register 6 IFCR6 6 R W 0x0000_0000 on page 862 0x0068 Identifier filter control register 7 IFCR7 6 R W 0x0000_0000 o...

Страница 839: ...3 BF SFTM LBKM MME SBDT RBLM SLEEP INIT W Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 This field resets to 0 for LINFlex_0 and 1 for LINFlex_1 Figure 23 7 LIN control register 1 LINCR1 Table 23 3 LINCR1 fiel...

Страница 840: ...erved This bit can be written in Initialization mode only It is read only in Normal or Sleep mode SFTM 25 Self test Mode This bit controls the Self test mode For more details see Section 23 6 2 Self t...

Страница 841: ...ialization mode If the SLEEP bit is reset LINFlex enters Normal mode when clearing the INIT bit see Table 23 6 Table 23 4 Checksum bits configuration CFD CCD LINCFR Checksum sent 1 1 Read Write None 1...

Страница 842: ...descriptions Field Description 0 15 Reserved SZIE 16 Stuck at Zero Interrupt Enable 0 No interrupt when SZF bit in LINESR or UARTSR is set 1 Interrupt generated when SZF bit in LINESR or UARTSR is set...

Страница 843: ...set DBFIE 27 Data Buffer Full Interrupt Enable 0 No interrupt when buffer data register is full 1 Interrupt generated when data buffer register is full DBEIE 28 Data Buffer Empty Interrupt Enable 0 N...

Страница 844: ...8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R LINS 0 3 0 0 RMB 0 RBSY RPS WUF DBFF DBEF DRF DTF HRF...

Страница 845: ...for a rising edge In Master mode Break transmission has been completed Break Delimiter transmission is ongoing 0101 Synch Field In Slave mode a valid Break Delimiter has been detected recessive state...

Страница 846: ...s empty It is set only when transmitting extended frames DFL 7 This bit must be cleared by software once buffer has been filled again in order to start transmission This bit is reset by hardware in In...

Страница 847: ...nter has matched the content of OC1 0 7 or OC2 0 7 in LINOCR If this bit is set and IOT bit in LINTCSR is set LINFlex moves to Idle state If LTOM bit in LINTCSR is set then OCF is cleared by hardware...

Страница 848: ...te received is discarded If RBLM is reset then the new byte overwrites the buffer It can be cleared by software 25 30 Reserved NF 31 Noise Flag This bit is set by hardware when noise is detected on a...

Страница 849: ...able This bit can be programmed only when the UART bit is set Note Transmission starts when this bit is set and when writing DATA0 in the BDRL register OP 28 Odd Parity 0 Sent parity is even 1 Sent pa...

Страница 850: ...ed the content of OC1 0 7 or OC2 0 7 in LINOCR An interrupt is generated if the OCIE bit in LINIER register is set PE3 18 Parity Error Flag Rx3 This bit indicates if there is a parity error in the cor...

Страница 851: ...ected a falling edge on the LINRX pin in Sleep mode This bit must be cleared by software It is reset by hardware in Initialization mode An interrupt i generated if WUIE bit in LINIER is set 27 28 Rese...

Страница 852: ...ut mode 0 LIN timeout mode header response and frame timeout detection 1 Output compare mode This bit can be set cleared in Initialization mode only IOT 22 Idle on Timeout 0 LIN state machine not rese...

Страница 853: ...23 14 LIN output compare register LINOCR Table 23 13 LINOCR field descriptions Field Description 0 15 Reserved OC2 0 7 16 23 Output compare 2 value These bits contain the value to be compared to the v...

Страница 854: ...he reset value is the 0x2C 44 corresponding to THeader_Maximum Setting MME bit in LINSR changes HTO 0 6 value to 0x1C 28 HTO 0 6 can be written only in Slave mode Address Base 0x0024 Access User read...

Страница 855: ...18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 DIV_M 0 12 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23 17 LIN integer baud rate register LINIBRR Table 23 16 LINIBRR field descriptions Field D...

Страница 856: ...ure 23 18 LIN checksum field register LINCFR Table 23 18 LINCFR field descriptions Field Description 0 23 Reserved CF 0 7 24 31 Checksum bits When CCD bit in LINCR1 is cleared these bits are read only...

Страница 857: ...et by software to stop data reception if the frame does not concern the node This bit is reset by hardware once LINFlex has moved to idle state In Slave mode this bit can be set only when HRF bit in L...

Страница 858: ...a maximum of 8 bytes of data Identifier filters are compatible with DFL 0 2 only DFL 3 5 are provided to manage extended frames DIR 22 Direction This bit controls the direction of the data field 0 LI...

Страница 859: ...0 0 Figure 23 21 Buffer data register LSB BDRL Table 23 21 BDRL field descriptions Field Description DATA3 0 7 0 7 Data Byte 3 Data byte 3 of the data field DATA2 0 7 8 15 Data Byte 2 Data byte 2 of...

Страница 860: ...0x0040 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0...

Страница 861: ...ACT 5 0 Filters 10 and 11 are deactivated 1 Filters 10 and 11 are activated FACT 6 0 Filters 12 and 13 are deactivated 1 Filters 12 and 13 are activated FACT 7 0 Filters 14 and 15 are deactivated 1 Fi...

Страница 862: ...Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23 25 Identifier filter mode register IFMR Table 23 26 IFMR field descriptions Field Description IFM Filter mode 0 Filters 2n and 2n 1 are in identifier li...

Страница 863: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 23 26 Identifier filter control register IFCR2n Table 23 28 IFCR2n field descriptions Field Description 0 18 Reserved DFL 0 2 19 21 Data Field Length These bits defi...

Страница 864: ...0 0 0 0 0 0 Figure 23 27 Identifier filter control register IFCR2n 1 Table 23 29 IFCR2n 1 field descriptions Field Description 0 18 Reserved DFL 0 2 19 21 Data Field Length These bits define the numbe...

Страница 865: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SZIE 0 OCIE 0 BEIE 0 CEIE 0 HEIE 0 0 0 FEIE 0 BOIE 0 LSIE 0 WUIE 0 DBFIE 0 DBEIE 0 DRIE 0 DTIE 0 HRIE 0 8 LINSR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LINS0 0 LIN...

Страница 866: ...0 HTO3 1 HTO4 1 HTO5 0 HTO6 0 24 LINFBRR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV_F0 0 DIV_F1 0 DIV_F2 0 DIV_F3 0 28 LINIBRR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Страница 867: ...DATA71 0 DATA72 0 DATA73 0 DATA74 0 DATA75 0 DATA76 0 DATA77 0 DATA60 0 DATA61 0 DATA62 0 DATA63 0 DATA64 0 DATA65 0 DATA66 0 DATA67 0 DATA50 0 DATA51 0 DATA52 0 DATA53 0 DATA54 0 DATA55 0 DATA56 0 DA...

Страница 868: ...FL0 0 DFL1 0 DFL2 0 DIR 0 CCS 0 0 0 ID0 0 ID1 0 ID2 0 ID3 0 ID4 0 ID5 0 50 58 60 68 70 78 80 88 IFCR2n 1 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DFL0 0 DFL1 0 DFL2 0 DIR 0 CCS 0 0 0 ID0 0 ID...

Страница 869: ...parity is set if the modulo 2 sum of the 7 data bits is 1 An odd parity is cleared in this case Figure 23 28 UART mode 8 bit data frame 9 bit frames The 9th bit is a parity bit Even Odd Parity can be...

Страница 870: ...he current reception is completed and no further reception can be invoked until RXEN is set If a parity error occurs during reception of any byte then the corresponding PEx bit in the UARTSR is set No...

Страница 871: ...Master sending a header The header is transmitted by the Master task while the data is transmitted by the Slave task of a node To transmit a header with LINFlex the application must set up the identif...

Страница 872: ...or handling It is possible to handle frames with a Response size larger than 8 bytes of data extended frames If the data field length in the BIDR is configured with a value higher than 8 data bytes th...

Страница 873: ...NFlex receives the identifier the HRF bit in the LINSR is set and if the HRIE bit in the LINIER is set an RX interrupt is generated The software must read the received identifier in the BIDR fill the...

Страница 874: ...the data by means of the identifier To avoid this and to ease the access to the SRAM locations the LINFlex controller provides a Filter Match Index This index value is the number of the filter that ma...

Страница 875: ...y time during a data field the current header or data is discarded and the state machine synchronizes on this new break 23 8 2 2 7 Valid message A received or transmitted message is considered as vali...

Страница 876: ...rs are associated with mask registers specifying which bits of the identifier are handled as must match or as don t care For the bit mapping and registers organization please refer to Figure 23 30 Fig...

Страница 877: ...r than 1 5 This feature compensates a fperiph_set_1_clk deviation up to 14 as specified in LIN standard Table 23 32 Filter to interrupt vector correlation Number of active filters Number of active fil...

Страница 878: ...s in the LINFBRR If LASE bit 1 then LFDIV is automatically updated at the end of each LIN Synch Field Three internal registers not user accessible manage the auto update of the LINFlex divider LFDIV L...

Страница 879: ...LIN timeout mode Setting the LTOM bit in the LINTCSR enables the LIN timeout mode The LINOCR becomes read only and OC1 0 7 and OC2 0 7 output compare values in the LINOCR are automatically updated by...

Страница 880: ...value is fixed to HTO 0 6 OC1 0 7 checks THeader and TResponse and OC2 0 7 checks TFrame refer to Figure 23 33 When LINFlex moves from Break state to Break Delimiter state refer to Section 23 7 2 3 L...

Страница 881: ...RF HRIE RXI 1 1 In Slave mode if at least one filter is configured as TX and enabled header received interrupt vector is RXI or TXI depending on the value of identifier received Data Transmitted inter...

Страница 882: ...LIN Controller LINFlex MPC5606S Microcontroller Reference Manual Rev 7 880 Freescale Semiconductor...

Страница 883: ...ermissions defined in single descriptor word Processors have separate read write execute attributes for supervisor and user accesses Non processor masters have read write attributes Hardware assisted...

Страница 884: ...ductor Figure 24 1 AHB_MPU block diagram ahb_mpu ips_wdata ips_addr decode mux IPS Bus 31 0 control rgd0 rgd1 rgd n 1 hit_b start end error ips_rdata 31 0 hit_b start end error error_detail EDRn error...

Страница 885: ...or details and Section 24 5 Application information for an example Support for 3 AHB slave port connections flash controller system ram controller and IPS peripherals bus MPU hardware continuously mon...

Страница 886: ...y register or a read of a write only register generate an IPS error termination Finally the programming model allocates space for an MPU definition with 8 region descriptors and up to 3 AHB slave port...

Страница 887: ...on Descriptor 10 128 R W on page 888 0x04B0 MPU_RGD11 MPU Region Descriptor 11 128 R W on page 888 0x04C0 0x07FF Reserved 0x0800 MPU_RGDAAC0 MPU RGD Alternate Access Control 0 32 R W on page 893 0x080...

Страница 888: ...captured error contained in the MPU_EARn and MPU_EDRn registers The individual bit is set when the hardware detects an error and records the faulting address and attributes It is cleared when the corr...

Страница 889: ...aded upon the occurrence of each protection violation Offset MPU_Base 0x010 MPU_EAR0 MPU_Base 0x018 MPU_EAR1 MPU_Base 0x020 MPU_EAR2 MPU_Base 0x028 MPU_EAR3 Access Read Read Read Read 0 1 2 3 4 5 6 7...

Страница 890: ...U_EDRn register contains a captured error and the EACD field is all zeroes this signals an access that did not hit in any region descriptor All non zero EACD values signal references that hit in a reg...

Страница 891: ...ber defined as the AHB hmaster 3 0 signal For the processor privilege rights there are three flags associated with this function read write execute In this context these flags follow the traditional d...

Страница 892: ...RGDn Word2 Table 24 7 MPU_RGDn Word2 field descriptions Field Description 0 M7RE Bus master 7 read enable If set this flag allows bus master 7 to perform read operations If cleared any attempted read...

Страница 893: ...allowed but no execute 0b11 Same access controls as that defined by M2UM for user mode 17 19 M2UM Bus master 2 user mode access control This 3 bit field defines the access controls for bus master 2 w...

Страница 894: ...ded If only the access controls are being updated this operation should be performed by writing to MPU_RGDAACn Alternate Access Control n as stores to these locations do not affect the descriptor s va...

Страница 895: ...etermination If a bit in the PIDMASK is set then the corresponding bit of the PID is ignored in the comparison This field is combined with the PID and included in the region hit determination if MPU_R...

Страница 896: ...access controls as that defined by M3UM for user mode 11 13 M3UM Bus master 3 user mode access control This 3 bit field defines the access controls for bus master 3 when operating in user mode The M3...

Страница 897: ...ster 1 when operating in user mode The M1UM field consists of three independent bits enabling read write and execute permissions r w x If set the bit allows the given access type to occur if cleared a...

Страница 898: ...nsibility to properly load appropriate values into these fields of the region descriptor In addition to this the optional process identifier is examined against the region descriptor s PID and PIDMASK...

Страница 899: ...error is reported The third condition reflects that priority is given to permission granting over access denying for overlapping regions as this approach provides more flexibility to system software i...

Страница 900: ...xisting region descriptor need to change a 32 bit write to the alternate version of the access control word MPU_RGDAACn would typically be performed Recall writes to the region descriptor using this a...

Страница 901: ...Memory Protection Unit MPU MPC5606S Microcontroller Reference Manual Rev 7 Freescale Semiconductor 899...

Страница 902: ...Memory Protection Unit MPU MPC5606S Microcontroller Reference Manual Rev 7 900 Freescale Semiconductor...

Страница 903: ...01 Chapter 25 Mode Entry Module MC_ME 25 1 Introduction 25 1 1 Overview The MC_ME controls the device mode and mode transition sequences in all functional states It also contains configuration control...

Страница 904: ...ocontroller Reference Manual Rev 7 902 Freescale Semiconductor Figure 25 1 MC_ME block diagram Registers Platform Interface core MC_ME MC_RGM FXOSC FMPLL0 FMPLL1 FIRC MC_CGM MC_PCU peripherals Flashes...

Страница 905: ...user modes are modes such as Run0 3 Halt Stop and Standby which can be configured to meet the application requirements in terms of energy management and available processing power The modes DRUN Safe...

Страница 906: ...p system reset assertion Safe via software or hardware failure other Run0 3 modes Halt Stop Standby via software Halt This is a reduced activity low power mode during which the clock to the core is di...

Страница 907: ...0xC3FD_C030 ME_RUN0_MC Run0 Mode Configuration word read write 0xC3FD_C034 ME_RUN1_MC Run1 Mode Configuration word read write 0xC3FD_C038 ME_RUN2_MC Run2 Mode Configuration word read write 0xC3FD_C03...

Страница 908: ...0xC3FD_C0ED ME_PCTL45 I2C_DMA1 Control byte read write 0xC3FD_C0EE ME_PCTL46 I2C_DMA2 Control byte read write 0xC3FD_C0EF ME_PCTL47 I2C_DMA3 Control byte read write 0xC3FD_C0F0 ME_PCTL48 LIN_FLEX0 Co...

Страница 909: ...E_MCTL R TARGET_MODE 0 0 0 0 0 0 0 0 0 0 0 0 W R 1 0 1 0 0 1 0 1 0 0 0 0 1 1 1 1 W KEY 0xC3FD_C008 ME_ME R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R 0 0 STANDBY 0 0 STOP 0 HALT RUN3 RUN2 RUN1 RUN0 DRUN SAFE...

Страница 910: ...C Reserved 0xC3FD_C020 ME_RESET_MC R 0 0 0 0 0 0 0 0 PDO 0 0 MVRON DFLAON CFLAON W R 0 0 0 0 0 0 0 0 FMPLL1ON FMPLL0ON FXOSCON FIRCON SYSCLK W 0xC3FD_C024 ME_TEST_MC R 0 0 0 0 0 0 0 0 PDO 0 0 MVRON DF...

Страница 911: ...0 0 0 0 0 0 0 0 FMPLL1ON FMPLL0ON FXOSCON FIRCON SYSCLK W 0xC3FD_C040 ME_HALT_MC R 0 0 0 0 0 0 0 0 PDO 0 0 MVRON DFLAON CFLAON W R 0 0 0 0 0 0 0 0 FMPLL1ON FMPLL0ON FXOSCON FIRCON SYSCLK W 0xC3FD_C044...

Страница 912: ...FD_C060 ME_PS0 R S_BAM 0 0 0 0 0 0 0 S_DMA_CH_MUX 0 0 0 0 0 S_FlexCAN1 S_FlexCAN0 W R 0 0 0 0 0 S_QUADSPI 0 0 0 S_QUADSPI S_DSPI1 S_DSPI0 0 0 0 0 W 0xC3FD_C064 ME_PS1 R S_DCU S_SGL S_LCD S_CANSampler...

Страница 913: ...0 0 0 0 0 0 0 0 0 0 0 0 0 W R 0 0 0 0 0 0 0 0 S_CMU0 0 0 0 0 0 0 0 W 0xC3FD_C070 Reserved 0xC3FD_C074 0xC3FD_C07C Reserved 0xC3FD_C080 0xC3FD_C09C ME_RUN_PC0 7 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R 0...

Страница 914: ...lobal mode status 0xC3FD_C0C0 0xC3FD_C14C ME_PCTL0 143 R 0 DBG_F LP_CFG RUN_CFG 0 DBG_F LP_CFG RUN_CFG W R 0 DBG_F LP_CFG RUN_CFG 0 DBG_F LP_CFG RUN_CFG W 0xC3FD_C150 0xC3FD_FFFC Reserved Address 0xC3...

Страница 915: ...andby mode the power sequence driver and all pads except those mapped on wakeup lines are not powered and therefore high impedance Wakeup lines configuration remains unchanged S_MVR Main voltage regul...

Страница 916: ...not stable 1 fast internal RC oscillator 16MHz is providing a stable clock S_SYSCLK System clock switch status These bits specify the system clock currently used by the system 0000 16MHz int RC osc 0...

Страница 917: ...the Halt and Stop modes on hardware exit events these are updated with the appropriate Run0 3 mode value 0000 Reset 0001 Test 0010 Safe 0011 DRUN 0100 Run0 0101 Run1 0110 Run2 0111 Run3 1000 Halt 1001...

Страница 918: ...1 Stop mode is enabled HALT Halt mode enable 0 Halt mode is disabled 1 Halt mode is enabled RUN3 Run3 mode enable 0 Run3 mode is disabled 1 Run3 mode is enabled RUN2 Run2 mode enable 0 Run2 mode is d...

Страница 919: ...1 Invalid mode configuration interrupt is pending Note The I_ICONF bit will not detect that modes that select a PLL to be active also have the FXOSC enabled Therefore always ensure that any mode that...

Страница 920: ...NF M_IMODE M_SAFE M_MTC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25 6 Interrupt Mask Register ME_IM Table 25 8 Interrupt Mask Register ME_IM field descriptions Field Description M_ICONF Invalid...

Страница 921: ...e transition requested is illegal S_MRI Mode Request Illegal status This bit is set whenever the target mode requested is not a valid mode with respect to current mode It is cleared by writing a 1 to...

Страница 922: ...SCLK_SW DFLASH_SC CFLASH_SC CDP_PRPH_0_143 0 0 0 CDP_PRPH_96_127 CDP_PRPH_64_95 CDP_PRPH_32_63 CDP_PRPH_0_31 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 25 8 Debug Mode Transition Status Register M...

Страница 923: ...eted their state changes A secondary system clock source is a system clock source other than FIRC FXOSC or FMPLL0 0 No state change is taking place 1 A state change is taking place SYSCLK_S W System C...

Страница 924: ...en requested to have their clocks disabled have entered the state in which their clocks may be disabled 0 No peripheral clock disabling is pending 1 Clock disabling is pending for at least one periphe...

Страница 925: ...read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 PDO 0 0 MVRON DFLAON CFLAON W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0...

Страница 926: ...yte and half word write accesses are not allowed to this register NOTE The values of FXOSCON FMPLL1ON CFLAON and DFLAON are retained through Standby mode Address 0xC3FD_C02C Access Supervisor read wri...

Страница 927: ...s 0xC3FD_C030 0xC3FD_C03C Access Supervisor read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 PDO 0 0 MVRON DFLAON CFLAON W Reset 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 16 17 18 19 20 21 22...

Страница 928: ...r read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 PDO 0 0 MVRON DFLAON CFLAON W Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0...

Страница 929: ...1 Main voltage regulator is switched on DFLAON Data flash power down control This bit specifies the operating mode of the data flash after entering this mode 00Reserved 01 Data flash is in power down...

Страница 930: ...reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled Address 0xC3FD_C060 Access Supervis...

Страница 931: ...details Address 0xC3FD_C064 Access Supervisor read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R S_DCU S_SGL S_LCD S_CANSAMPLER 0 0 0 S_GAUGEDRIVER 0 0 0 0 0 0 S_LIN_FLEX1 S_LIN_FLEX0 W Reset 0 0 0 0 0 0 0...

Страница 932: ...0 S_PIT_RTI S_RTC_API S_MC_PCU S_MC_RGM S_MC_CGM S_MC_ME S_SSCM 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 S_CFLASH1 0 0 S_eMIOS1 S_eMI...

Страница 933: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 RUN3 RUN2 RUN1 RUN0 DRUN SAFE TEST RESET W Reset 0 0 0 0 0 0 0 0...

Страница 934: ...4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 STANDBY 0 0 STOP 0 HALT 0 0 0 0 0 0 0 0 W...

Страница 935: ...Peripheral state depends on RUN_CFG LP_CFG bits and the device mode 1 Peripheral is frozen if not already frozen in device modes Note This feature is useful to freeze the peripheral state while enter...

Страница 936: ...status register ME_GS to verify when the mode has been correctly entered and the transition process has completed For a description of valid mode requests please refer to Section 25 4 5 Mode transiti...

Страница 937: ...th the default configuration selecting the 16MHz int RC osc as the system clock This mode is intended to be used by software To initialize all registers as per the system needs To execute small routin...

Страница 938: ...esting a change to Safe before requesting another mode change As long as a Safe event is active the system remains in the Safe mode and no write access is allowed to the ME_MCTL register This mode is...

Страница 939: ...cur a Run0 3 mode transition request is generated The mode configuration information for these modes is provided by ME_RUN0 3_MC registers In these modes the flashes all clock sources and the system c...

Страница 940: ...ode The device enters this mode on the following events From one of the Run0 3 modes when the TARGET_MODE bit field of the ME_MCTL register is written with 1010 As soon as any of the above events occu...

Страница 941: ...BY_MC register In this mode the power supply is turned off for most of the device By default the only parts of the device that are still powered during this mode are pads mapped on wakeup lines and po...

Страница 942: ...nsition status bit S_MTRANS of the ME_GS register A Reset mode requested via the ME_MCTL register is passed to the MC_RGM which generates a global system reset and initiates the reset sequence The Res...

Страница 943: ...uest after closing its internal activity The MC_ME then disables the corresponding clock s to this peripheral In the case of a Safe mode transition request the MC_ME does not wait for the peripherals...

Страница 944: ...25 4 3 6 Clock sources switch on On completion of the Processor Low Power mode entry the MC_ME controls all clock sources that affect the system clock based on the clock source ON bits of the ME_ curr...

Страница 945: ...off in device low power modes then during the exit sequence the flash is kept in its low power state and is switched on only when the Main Voltage Regulator Switch On process has completed WARNING It...

Страница 946: ...stopped state This step is executed only after the Processor and memory clock enable process is completed 25 4 3 15 System clock switching Based on the SYSCLK bit field of the ME_ current mode _MC an...

Страница 947: ...ven mode 25 4 3 16 Power Domain 2 Switch Off Based on the device mode and the MC_PCU s power configuration register PCU_PCONF2 the power domain 2 is controlled by the MC_PCU If a mode change translate...

Страница 948: ...0 This step is executed only after System clock switching process is completed in order not to lose the current system clock during mode transition FMPLL0 Switch Off as the input reference clock of th...

Страница 949: ...ted by the MC_PCU after which it may be switched off depending on the FIRCON bit of the ME_STANDBY_MC register 25 4 3 22 Current mode update The current mode status bit field S_CURRENT_MODE of the ME_...

Страница 950: ...upt wakeup event Peripheral Clocks Disable Clock sources Switch On System Clock Switching Main VREG Switch On FLASH Switch On Pad Processor Low Power Processor and PAD Peripheral Clocks Enable FLASH S...

Страница 951: ...elds are reserved MVREG must be on if any of the following is active FMPLL0 CFLASH DFLASH System clock configurations marked as reserved may not be selected Configuration 1111 for the SYSCLK bit field...

Страница 952: ...llegal status bit S_MTI of the ME_IMTS register is set This condition is detected only when the proper key mechanism is followed while writing the ME_MCTL register Otherwise the write operation is ign...

Страница 953: ...h a particular clock gating policy determined by two groups of peripheral configuration registers The run peripheral configuration registers ME_RUN_PC0 7 are chosen only during the software running mo...

Страница 954: ...ed Figure 25 26 MC_ME Application Example Flow Diagram START of mode change config for target mode okay write ME_ target mode _MC ME_RUN_PC0 7 ME_LP_PC0 7 and ME_PCTL0 143 registers N Y write ME_MCTL...

Страница 955: ...Mode Entry Module MC_ME MPC5606S Microcontroller Reference Manual Rev 7 Freescale Semiconductor 953...

Страница 956: ...Mode Entry Module MC_ME MPC5606S Microcontroller Reference Manual Rev 7 954 Freescale Semiconductor...

Страница 957: ...the IEEE ISTO 5001 2003 standard The development support provided includes program trace watchpoint messaging ownership trace watchpoint triggering processor overrun control run time access to the MCU...

Страница 958: ...wnership trace by providing visibility of which process ID or operating system task is activated An ownership trace message is transmitted when a new process task is activated allowing the development...

Страница 959: ...he Nexus2 controller clocks are gated off While the core is in this state it is not possible to perform Nexus read write operations 26 4 Modes of operation The NDI block is in reset when the TAP contr...

Страница 960: ...mory mapped resources when censorship is enabled 26 4 2 3 Stop mode Stop mode logic is implemented in the Nexus port controller NPC When a request is made to enter Stop mode the NDI block completes mo...

Страница 961: ...rs and describes the registers and their bit fields 26 6 2 1 Nexus Device ID Register DID The NPC device identification register shown in Figure 26 3 allows the part revision number design center part...

Страница 962: ...MCKO is enabled can produce unpredictable results Reg Index 0 Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R Part Revision Number 1 1 Part Revision Number default value is 0x0 for the...

Страница 963: ...f the auxiliary output port uses the full MDO port or a reduced MDO port to transmit messages 0 A subset of MDO pins is used to transmit messages 1 All MDO pins are used to transmit messages MCKO_GT M...

Страница 964: ...N Low Power Debug Enable The LP_DBG_EN bit enables debug functionality to support entry and exit from low power sleep and Stop modes 0 Low power debug disabled 1 Low power debug enabled SLEEP_SYNC Sle...

Страница 965: ...guration 4 MDO pins 1 2 MCK_DIV 1 0 1 MCKO Clock Divide Ratio see note 1 00 MCKO is 1 processor clock frequency 01 MCKO is 1 2 processor clock frequency 10 MCKO is 1 4 processor clock frequency 11 MCK...

Страница 966: ...ead write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R EWC 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset...

Страница 967: ...4 Access User read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R DBG LPS LPC CHK 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0...

Страница 968: ...0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R AC RW SZ MAP PR 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R CNT ERR DV W Reset 0 0 0 0 0 0 0 0 0 0 0...

Страница 969: ...SZ 30 ERR Read Write Access Error See Table 26 9 31 DV Read Write Access Data Valid See Table 26 9 Table 26 9 Read Write Access Status Bit Encoding Read Action Write Action ERR DV Read access has not...

Страница 970: ...ails the watchpoint trigger register fields Nexus Reg 0x000A Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R RWD 0 15 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24...

Страница 971: ...ry consists of setting the low power mode handshake bit in the port control register read by the debugger via the lp_sync_in output The debugger acknowledges that the transition into a low power mode...

Страница 972: ...et to bring the NDI out of the reset state the loading of a specific instruction in the JTAG controller JTAGC block is required to grant the NDI ownership of the TAP Each Nexus client has its own JTAG...

Страница 973: ...s an output clock to the development tools used for the timing of MSEO and MDO pin functions MCKO is derived from the system clock and its frequency is determined by the value of the MCKO_DIV field in...

Страница 974: ...system clock periods EVTO sharing is active as long as the NDI is not in reset 26 7 7 Debug mode control On MPC5606S program breaks can be requested either by using the EVTI pin as a break request or...

Страница 975: ...nnels This device has one PIT module with four Timer Channels PIT channels 0 through 3 These are connected to the Trigger input 0 through 3 of the DMA MUX Figure 27 1 shows the PIT block diagram Figur...

Страница 976: ...here the Base Address is defined at the MCU level and the Address Offset is defined at the module level NOTE Reserved registers will read as 0 writes will have no effect Table 27 1 PIT memory map Addr...

Страница 977: ...upts Offset Base 0x000 Access Read Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31...

Страница 978: ...ions Field Description TSVn Time Start Value Bits These bits set the timer start value The timer will count down until it reaches 0 then it will generate an interrupt and load this register value agai...

Страница 979: ...ntrol Register see Figure 27 2 Offset Channel_base 0x08 Access Read Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20...

Страница 980: ...timer can be read via the CVAL registers The counter period can be restarted by first disabling then enabling the timer with the TEN bit see Figure 27 7 The counter period of a running timer can be mo...

Страница 981: ...ts All of the timers support interrupt generation Refer to the MCU specification for related vector addresses and priorities Timer interrupts can be disabled by setting the TIE bits to zero The timer...

Страница 982: ...s means that LDVAL1 with 0003E7FF hex and LDVAL3 with 0016E35F hex The interrupt for Timer 1 is enabled by setting TIE in the TCTRL1 register The timer is started by writing a 1 to bit TEN in the TCTR...

Страница 983: ...IDGE Supports the slave interface signals This interface is only meant for slave peripherals Supports 32 bit slave peripherals Byte halfword and word reads and writes are supported to each 28 1 3 Mode...

Страница 984: ...at contain readable writable control and status registers The system bus master reads and writes these registers through the PBRIDGE The PBRIDGE generates module enables the module address transfer at...

Страница 985: ...domain reaches its operational voltage Power domains are controlled on a device mode basis For each mode software can configure whether a power domain is connected to the supply voltage startup state...

Страница 986: ...tandby for further mode details please see Chapter 25 Mode Entry Module MC_ME Power states updating on each mode change and on system wakeup A handshake mechanism for power state changes thus guarante...

Страница 987: ...word read 0xC3FE_8004 PCU_PCONF1 Power Domain 1 Configuration word read 0xC3FE_8008 PCU_PCONF2 Power Domain 2 Configuration word read write 0xC3FE_8040 PCU_PSTAT Power Domain Status Register word read...

Страница 988: ...C 0xC3FE_803C Reserved 0xC3FE_8040 PCU_PSTAT R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W R PD2 PD1 PD0 W 0x044 0x07C Reserved 0xC3FE_8080 0xC3FE_80FC VREG registers 0xC3FE_8100 0xC3FE_BFFC Reserved Address 0x...

Страница 989: ...wer domain off 1 Power domain on SAFE Power domain control during Safe mode 0 Power domain off 1 Power domain on DRUN Power domain control during DRUN mode 0 Power domain off 1 Power domain on RUN0 Po...

Страница 990: ...about Standby mode please refer to Section 29 4 4 2 Standby mode transition 29 3 2 3 Power Domain 2 Configuration Register PCU_PCONF2 This register defines for power domain 2 whether it is on or off i...

Страница 991: ...Reset Power On Reset After any reset the SoC will transition to the Reset mode during which all power domains are powered up see the MC_ME chapter Once the reset sequence has been completed the DRUN m...

Страница 992: ...r power domain 2 onwards The settings for power domains 0 and 1 cannot be changed Therefore power domains 0 and 1 remain connected to the power supply for all modes beside Standby Figure 29 6 shows an...

Страница 993: ...ystem wakeup On exiting the Standby mode all power domains are powered up according to the settings in the PCU_PCONFn registers and the DRUN mode is entered In DRUN mode at least power domains 0 and 1...

Страница 994: ...er a power saving state No software configuration is required to enable this power saving state While a memory is residing in this state an increased power saving is achieved Data in the memories is r...

Страница 995: ...over a signal name indicates that the signal is active low Active low signals are referred to as asserted when they are logic 0 and negated when they are logic 1 0x0F Hexadecimal numbers 0b0011 Binar...

Страница 996: ...mines the idle state of the SCK signal Deserialize To convert data from a serial format to a parallel format Drain To remove entries from a FIFO by software or hardware Field Two or more register bits...

Страница 997: ...SPI Command is part of each TX FIFO entry specifying the parameters for the transmission of that specific entry SPI Master mode The QuadSPI is set up as SPI master to communicate with external SPI sl...

Страница 998: ...data rdata QSPI_IF_core QSPI_IF_sclk cmd txdata ready tx_acc rxdata ready rx_acc events RX Buffer TX Buffer SFAR ICR address register instruct register command_build and buffer control define rd_data...

Страница 999: ...tributes on a per frame basis Parameterized number of transfer attribute registers from two to eight Serial clock with programmable polarity and phase Various programmable delays Programmable serial f...

Страница 1000: ...ection 30 5 2 2 Master mode for a detailed description In this mode the QuadSPI uses the system clock as its timing reference 30 2 3 2 SPI Slave mode The Slave mode allows the QuadSPI to communicate w...

Страница 1001: ...to SPI or vice versa may not be possible for all flash memories Check I O compatibility before using this Table 30 4 Signal properties Signal name Function and direction SPI Master mode SPI Slave mode...

Страница 1002: ...signal that allows a SPI master to select the QuadSPI as the target for transmission In Serial Flash mode this signal is the chip select for the serial flash device 30 3 2 2 PCS 3 1 Peripheral Chip S...

Страница 1003: ...I Slave mode SCK is an input from an external bus master In Serial Flash mode this signal is the serial clock output to the serial flash device and is based on the auxiliary clock 30 4 Memory map and...

Страница 1004: ...0x104 Instruction Code Register QSPI_ICR QSPI_BASE 0x108 Sampling Register QSPI_SMPR QSPI_BASE 0x10C RX Buffer Status Register QSPI_RBSR QSPI_BASE 0x110 QSPI_BASE 0x148 RX Buffer Data Registers 0 14...

Страница 1005: ...e of the registers at least a 16 32 bit wide write access is required to ensure correct operation This write access requirement is stated in the detailed register description for each register affecte...

Страница 1006: ...aster Slave mode Select Only applicable if QMODE is cleared The MSTR bit configures the QuadSPI for either SPI Master mode or SPI Slave mode 0 QuadSPI is in SPI Slave mode 1 QuadSPI is in SPI Master m...

Страница 1007: ...uadSPI in a software controlled power saving state See Section 30 5 4 Power saving features and Section 30 5 2 1 Start and Stop of SPI Transfers for more information 0 Enable QuadSPI clocks 1 Allow ex...

Страница 1008: ...block is in SPI Master or SPI Slave mode When this bit is set the QuadSPI block is in Serial Flash mode 0 Module is in SPI Master or SPI Slave mode 1 Module is in SFM mode VMID VMID Vendor Model ID On...

Страница 1009: ...is configured as a SPI Master the CTAS field in the command portion of the TX FIFO entry selects which of the QSPI_CTAR register is used When the QuadSPI is configured as a SPI bus Slave the QSPI_CTA...

Страница 1010: ...k polarities without stopping the QuadSPI can cause errors in the transfer due to the peripheral device interpreting the switch of clock polarity as a valid clock edge 0 The inactive state value of SC...

Страница 1011: ...alues The PCS to SCK Delay is a multiple of the system clock period and it is computed according to the following equation Eqn 30 1 See Section 30 5 2 7 2 PCS to SCK Delay tCSC for more details ASC Af...

Страница 1012: ...60 40 1 1 11 57 43 Table 30 13 Transfer Frame Size FMSZ Framesize FMSZ Framesize 0000 Reserved 1000 9 0001 Reserved 1001 10 0010 Reserved 1010 11 0011 4 1011 12 0100 5 1100 13 0101 6 1101 14 0110 7 11...

Страница 1013: ...6384 0110 128 1110 32768 0111 256 1111 65536 Table 30 16 After Transfer Scaler DT Delay after Transfer Scaler Value DT Delay after Transfer Scaler Value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 20...

Страница 1014: ...at the end of the frame transfer The TCF bit remains set until cleared by software 0 Transfer not complete 1 Transfer complete TXRXS TX RX Status The TXRXS bit reflects the status of the QuadSPI See S...

Страница 1015: ...ethod for the QuadSPI to request that entries be removed from the RX FIFO The bit is set while the RX FIFO is not empty The RFDF bit can be cleared by host software or an acknowledgement from the DMA...

Страница 1016: ...isabled 1 EOQF interrupt requests are enabled TFUF_RE TX FIFO Underrun IRQ Enable The TFUF_IE bit enables the TFUF flag in the QSPI_SPISR to generate an interrupt request 0 TFUF interrupt requests are...

Страница 1017: ...quests are disabled 1 RFDF interrupt requests or DMA requests are enabled RFDF_DIRS RX FIFO Drain DMA or Interrupt Request Select The RFDF_DIRS bit selects between generating a DMA request or an inter...

Страница 1018: ...transfer attributes for the associated SPI frame The field is used only in SPI Master mode In SPI Slave mode QSPI_CTAR0 is used The table below shows how the CTAS values map to the QSPI_CTAR register...

Страница 1019: ...Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R RXDATA W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 8 POP RX FIFO Register QSPI_POPR Table 30 21 QSPI_POPR...

Страница 1020: ...of bits used from this register depend on the instruction code of the SFM command See Section 30 5 3 SFM Serial Flash mode for details Table 30 22 QSPI_TXFRn field descriptions Field Description TXCM...

Страница 1021: ...with that instruction code if this code is supported by the module see 30 7 1 Supported Instruction Codes in Winbond Devices The QSPI_ICR register is writable only in SFM mode Refer to Section 30 5 3...

Страница 1022: ...0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R ICO IC W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 12 Instruction Code Register QSPI_ICR Table 30 25 QSPI_ICR field descriptions...

Страница 1023: ...Two clock cycles delay FSPHS Full Speed Phase selection Select the edge of the sampling clock valid for full speed commands 0 Select sampling at non inverted clock 1 Select sampling at inverted clock...

Страница 1024: ...20 21 22 23 24 25 26 27 28 29 30 31 R RDBFL 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 14 RX Buffer Status Register QSPI_RBSR Table 30 27 QSPI_RBSR field descriptions Field Des...

Страница 1025: ...0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R RXDATA 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 30 15 RX Buffer Data Registers 0 14 QSPI_RBDR0 QSPI_RBDR14 Table 30 28 QSPI_RBDR...

Страница 1026: ...bytes have been written into the TX Buffer by host accesses It is reset to 0 when a 1 is written into the QSPI_MCR CLR_TXF bit It is incremented on each write access to the QSPI_TBDR register by the...

Страница 1027: ...1 1 Figure 30 18 AMBA Control Register QSPI_ACR Table 30 31 QSPI_ACR field descriptions Field Description ARMB AMBA Read Mode Byte Instruction code option for ARIC for continuos mode Table 30 53 M7 M0...

Страница 1028: ...sserted when TX Buffer contains data RX Buffer Related Status Information RXFULL RX Buffer Full Asserted when RX Buffer is full RXNE RX Buffer Not Empty Asserted when RX Buffer contains data AHB Buffe...

Страница 1029: ...e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R1 1 When not in SFM mode all 0 s are read 0 0 0 0 TBFF TBUF 0 0 0 0 0 0 0 0 RBOF RBDF W w1c w1c w1c w1c Reset 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21...

Страница 1030: ...o the assertion of the IPAEF flag is ignored IPIEF IP Command Trigger during IP Access Error Flag Set on any of the following conditions A write access occurs to the QSPI_ICR register and the QSPI_SFM...

Страница 1031: ...I_SFMRSER Table 30 34 QSPI_SFMRSER field descriptions Field Description TBFIE TX Buffer Fill Interrupt Enable TBUIE TX Buffer Underrun Interrupt Enable RBDDE RX Buffer Drain DMA Enable Enables generat...

Страница 1032: ...order Refer to Table 30 35 below for details The available address range depends from the size of the external serial flash device Any access beyond the size of the external serial flash provides und...

Страница 1033: ...ails Serial Flash mode can be used for write or read accesses to an external serial flash device Serial Flash Write Data can be programmed into the flash of the serial flash device Refer to Section 30...

Страница 1034: ...RX FIFO Buffering Mechanism The interrupt and DMA request conditions are described in Section 30 5 2 10 SPI mode interrupt and DMA requests There are two different SPI modes Master mode and Slave mod...

Страница 1035: ...opped state no serial transfers are initiated in Master mode and no transfers are responded to in Slave mode The Stopped state is also a safe state for writing the various configuration registers of t...

Страница 1036: ...e bus master but clock polarity clock phase and numbers of bits to transfer must still be configured in the QuadSPI slave for proper communications with an external SPI master In SPI Slave mode the sl...

Страница 1037: ...rough the shift register Entries are transferred from the TX FIFO to the shift register and shifted out as long as there are valid entries in the TX FIFO Every time an entry is transferred from the TX...

Страница 1038: ...g the POP RX FIFO Register QSPI_POPR A read of the QSPI_POPR decrements the RX FIFO Counter by one Attempts to pop data from an empty RX FIFO are ignored the RX FIFO Counter remains unchanged The data...

Страница 1039: ...DT The Delay after Transfer is the length of time between negation of the PCS signal for a frame and the assertion of the PCS signal for the next frame See Figure 30 27 for an illustration of the Dela...

Страница 1040: ...sfer the delay between PCSS negation and PCS negation is selected by the PASC field in the QSPI_CTAR based on the following formula Eqn 30 6 Table 30 42 shows an example of how to compute the tpcssck...

Страница 1041: ...1 A modified transfer format is supported to allow for high speed communication with peripherals that require longer setup times The QuadSPI can sample the incoming data later than halfway through th...

Страница 1042: ...changes the data on their SO pins on the even numbered clock edges After the last clock edge occurs a delay of tASC is inserted before the master negates the PCS signals A delay of tDT is inserted bef...

Страница 1043: ...ew frame transfer can be initiated by the master 30 5 2 8 3 Modified SPI Transfer Format MTFE 1 CPHA 0 In this Modified Transfer Format both the Master and the Slave sample later in the SCK period tha...

Страница 1044: ...ys 4 30 5 2 8 4 Modified SPI Transfer Format MTFE 1 CPHA 1 Figure 30 30 shows the Modified Transfer Format for CPHA 1 Only the condition where CPOL 0 is described At the start of a transfer the QuadSP...

Страница 1045: ...lection Format provides the flexibility to handle both cases The Continuous Selection Format is enabled for both SPI modes by setting the CONT bit in the SPI Command When the CONT bit 0 the QuadSPI dr...

Страница 1046: ...s with CPHA 1 and CONT 1 Figure 30 32 Example of Continuous Transfer CPHA 1 CONT 1 Switching CTAR registers or changing which PCS signals are asserted between frames while using Continuous Selection c...

Страница 1047: ...ified or the Continuous SCK mode is terminated It is recommended that the baud rate is the same for all transfers made while using the Continuous SCK Switching clock polarity between frames while usin...

Страница 1048: ...as a flag bit in the SPI Status Register QSPI_SPISR and a Request Enable bit in the SPI Interrupt and DMA Request Select and Enable Register QSPI_SPIRSER The TX FIFO Fill Flag TFFF and RX FIFO Drain F...

Страница 1049: ...the RX FIFO is not empty The RX FIFO Drain Request is generated when the number of entries in the RX FIFO is not zero and the RFDF_RE bit in the QSPI_SPIRSER is asserted The RFDF_DIRS bit in the QSPI...

Страница 1050: ...following registers Read address of the serial flash into QSPI_SFAR refer to Section 30 4 3 11 Serial Flash Address Register QSPI_SFAR Instruction code options belonging to the IP Command into the QSP...

Страница 1051: ...The data are fetched from the TX Buffer It consists of 15 entries with 32 bit and is organized as a circular FIFO whose read pointer is incremented after each fetch When all data are transmitted the Q...

Страница 1052: ...l Buffers The data read out from the external serial flash device by the QuadSPI module are stored in the internal buffers Depending from the buffer to which the data from the external serial flash ha...

Страница 1053: ...dule from the serial flash the execution of the current command remains running with the AHB read access stalled As soon as the data from the requested address have been read by the QuadSPI module the...

Страница 1054: ...TX Buffer Operation for details about the assertion of the QSPI_SFMFR TBFF flag 30 5 3 5 2 Receive Buffer Drain Interrupt or DMA Request The Receive Buffer Drain IRQ derived from the QSPI_SFMFR RBDF f...

Страница 1055: ...0 5 3 5 5 Transaction Finished Interrupt Request The Transaction Finished IRQ indicates the completion of the current command It is masked by the QSPI_SFMSR TF_IE bit 30 5 3 6 TX Buffer Operation The...

Страница 1056: ...s not accessible The states of the interrupt and DMA request signals cannot be changed while in Stop mode Note that the following actions are illegal in SFM mode during the time starting with raising...

Страница 1057: ...ed to normal operation in SFM mode the execution of the first SFM command is deferred until the clock to drive that part of the module related to the serial flash device is available Depending from th...

Страница 1058: ...1 to the CLR_TXF bit in the QSPI_MCR Flush RX FIFO by writing a 1 to the CLR_RXF bit in the QSPI_MCR 9 Clear transfer count either by setting CTCNT bit in the command word of the first entry in the n...

Страница 1059: ...7 M 10 0 M 7 14 M 4 8 M 5 33 M 3 2 M 2 29 M 12 5 M 8 33 M 5 00 M 3 57 M 6 5 33 M 3 56 M 2 13 M 1 52 M 8 33 M 5 56 M 3 33 M 2 38 M 8 4 M 2 67 M 1 6 M 1 14 M 6 25 M 4 17 M 2 50 M 1 79 M 16 2 M 1 33 M 8...

Страница 1060: ...0 480 s For DSCK 0 1 2 SCK period For this value the value for the QuadSPI is 20ns Table 30 48 Delay values Bus Clock 64 MHz Bus clock 100 MHz Delay prescaler values Delay prescaler values 1 3 5 7 1...

Страница 1061: ...in and last in FIFO entries along with the FIFO Counter The TX FIFO is chosen for the illustration but the concepts carry over to the RX FIFO See Section 30 5 2 5 Transmit First In First Out TX FIFO...

Страница 1062: ...pth implementation specific 30 6 5 2 Address Calculation for the First in Entry and Last in Entry in the RX FIFO The memory address of the first in entry in the RX FIFO is computed by the following eq...

Страница 1063: ...mand the QSPI_SFMSR IPACC and the QSPI_SFMSR BUSY bits are asserted simultaneously immediately after the execution is started When the instruction on the serial flash device has been finished these bi...

Страница 1064: ...me is as follows During the execution of an IP Bus related command the running command can t be terminated by issuing another IP Bus or AHB Table 30 50 Overview of QSPI_SFMFR error flags Error categor...

Страница 1065: ...nto the QuadSPI Module for further details The commands ignored in case of command collision will not result in the assertion of the QSPI_SFMFR TFF flag It s up to the application to watch the error f...

Страница 1066: ...nsfer length is limited to e g 16 words when reading the serial flash in Quad I O mode Careful analysis of the DMA usage in the entire device containing the QuadSPI module is required to avoid RX Buff...

Страница 1067: ...A0 24 size D7 D0 32k Block Erase 52h A23 A0 24 64k Block Erase D8h A23 A0 24 Sector Erase 20h A23 A0 24 Chip Erase C7h 60h Erase Suspend 75h Erase Resume 7Ah Power down B9h High Performance mode A3h...

Страница 1068: ...nd documentation this command only supports a maximum clock speed of 50 MHz If the Serial Flash is operated at a higher clock frequency the clock frequency for this command must be decreased Refer to...

Страница 1069: ...in time at the QuadSPI sampling logic w r t internal reference clock Refer to Figure 30 36 for an overview of this scheme Figure 30 36 Serial Flash Sampling Clock Overview NOTE The arrival of the seri...

Страница 1070: ...serial flash device 3 Clock to data out delay of the external serial flash device including input and output delays 4 Wire delay of application PCB from the external serial flash device to the device...

Страница 1071: ...n absolute size to shift the point in time when the serial flash date get valid at the QuadSPI input For decreasing frequency of the serial flash clock the distance between the edges increases So for...

Страница 1072: ...Quad Serial Peripheral Interface QuadSPI MPC5606S Microcontroller Reference Manual Rev 7 1070 Freescale Semiconductor...

Страница 1073: ...rent reset sources and manages the reset sequence of the device It provides a register interface and the reset sequencer The different registers are available to monitor and control the device reset s...

Страница 1074: ...for further mode details please see the MC_ME chapter Short reset sequence configuration PAD 22 21 RESET Registers Platform Interface core MC_RGM MC_ME power on 1 2V low voltage detected power domain...

Страница 1075: ...usually non hardware error or dysfunction When a functional reset event occurs a partial reset sequence is applied to the device starting from Phase1 In this case most digital modules are reset norma...

Страница 1076: ...3 Memory map and register definition NOTE Any access to unused registers as well as write accesses to read only registers will Not change register content Cause a transfer error Table 31 1 MC_RGM Regi...

Страница 1077: ...TOP F_SOFT F_CORE F_JTAG W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c R F_POR F_LVD27 F_SWT F_LVD12_PD1 F_LVD12_PD0 W w1c w1c w1c w1c w1c 0xC3FE_4004 RGM_FERD RGM_DERD R D_EXR D_FLASH D_LVD45 D_CMU0_FHL...

Страница 1078: ...0xC3FE_4018 as a half word at address 0xC3FE_401A or as a byte at address 0xC3FE_401B 0xC3FE_4018 RGM_FESS RGM_STDBY R SS_EXR SS_FLASH SS_LVD45 SS_CMU0_FHL SS_CMU0_OLR SS_FMPLL0 SS_CHKSTOP SS_SOFT SS_...

Страница 1079: ...t 0 No external reset event has occurred since either the last clear or the last power on reset 1 An external reset event has occurred F_FLASH Flag for code or data flash fatal error 0 No code or data...

Страница 1080: ...ast power on reset 1 A checkstop reset event has occurred F_SOFT Flag for software reset 0 No software reset event has occurred since either the last clear or the last power on reset 1 A software rese...

Страница 1081: ...the reset s deassertion Table 31 4 Destructive Event Status Register RGM_DES field descriptions Field Description F_POR Flag for Power On reset 0 No power on event has occurred since the last clear d...

Страница 1082: ...ror event triggers a reset sequence 1 A code or data flash fatal error event generates either a Safe mode or an interrupt request depending on the value of RGM_FEAR AR_FLASH D_LVD45 Disable 4 5V low v...

Страница 1083: ...vent triggers a reset sequence 1 A software reset event generates either a Safe mode or an interrupt request depending on the value of RGM_FEAR AR_SOFT D_CORE Disable core reset 0 A core reset event t...

Страница 1084: ...power domain 1 event triggers a reset sequence 1 A 1 2V low voltage detected power domain 1 event generates either a Safe mode or an interrupt request depending on the value of RGM_DEAR AR_LVD12_PD1...

Страница 1085: ...e an interrupt request on a FXOSC frequency lower than reference event if the reset is disabled AR_FMPLL0 Alternate Request for FMPLL0 fail 0 Generate a Safe mode request on a FMPLL0 fail event if the...

Страница 1086: ...d AR_SWT Alternate Request for software watchdog timer 0 Generate a Safe mode request on a software watchdog timer event if the reset is disabled 1 Generate an interrupt request on a software watchdog...

Страница 1087: ...se3 skipping Phase1 and Phase2 SS_CMU0_ OLR Short Sequence for FXOSC frequency lower than reference 0 The reset sequence triggered by a FXOSC frequency lower than reference event will start from Phase...

Страница 1088: ...can be accessed in read in user mode Address 0xC3FE_401A Access Supervisor read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 BOOT_FROM_BKP_RAM 0 0 0 0 0 0 0 W reset 0 0 0 0 0 0 0 0 0...

Страница 1089: ...or event BE_LVD45 Bidirectional Reset Enable for 4 5V low voltage detected 0 RESET is asserted on a 4 5V low voltage detected event if the reset is enabled 1 RESET is not asserted on a 4 5V low voltag...

Страница 1090: ...o the next phase The state machine used to produce the reset sequence is shown in Figure 31 11 destructive resets all except some clock reset management yes yes external reset all except some clock re...

Страница 1091: ...ation 3 fast internal RC oscillator 16MHz clock cycles FIRC stable VREG voltage okay done duration 350 fast internal RC oscillator 16MHz clock cycles duration fast internal RC oscillator 16MHz clock c...

Страница 1092: ...ce the last enabled external or non shortened functional reset event 31 4 1 3 Phase2 Phase This phase is entered on exit from Phase1 The reset state machine exits Phase2 and enters Phase3 on verificat...

Страница 1093: ...ven destructive reset is disabled and the voltage goes below the digital functional threshold functionality can no longer be ensured and the reset may or may not be asserted An enabled destructive res...

Страница 1094: ...et When RGM_FESS SS_ functional reset is set the associated functional reset will trigger a reset sequence starting directly from the beginning of Phase3 skipping Phase1 and Phase2 This can be useful...

Страница 1095: ...ate a Safe mode interrupt request occurs during Phase0 it is ignored and the MC_RGM will not send any safe mode interrupt request to the MC_ME The same is true for masked functional reset events durin...

Страница 1096: ...Reset Generation Module MC_RGM MPC5606S Microcontroller Reference Manual Rev 7 1094 Freescale Semiconductor...

Страница 1097: ...nterrupt request 32 2 Features Features of the RTC include Four selectable counter clock sources 4 16 MHz FXOSC 128 kHz SIRC 32 KHz SXOSC 16 MHz FIRC Optional 512 prescaler and optional 32 prescaler 3...

Страница 1098: ...block diagram 0 1 2 CLKSEL 0 1 3 128 kHz SIRC 16 MHz FIRC 32 kHz CNTEN RTCCNT RTCVAL 10 21 RTCF RTCIE RTC interrupt offset reg 22 31 API wakeup load 22 31 APIVAL APIEN reset reset 32 bit counter sync...

Страница 1099: ...4 Modes of operation There are two functional modes of operation for the RTC normal operation and low power mode In normal operation all RTC registers can read or written and the input isolation is di...

Страница 1100: ...RTC Supervisor Control Register RTCSUPV The RTCSUPV register contains the SUPV bit which determines whether other registers are accessible in supervisor mode or user mode NOTE RTCSUPV register is acc...

Страница 1101: ...0 0 0 0 0 Table 32 2 RTCC field descriptions Field Description CNTEN Counter Enable The CNTEN bit enables the RTC counter Making CNTEN bit 1 b0 has the effect of asynchronously resetting synchronous r...

Страница 1102: ...ect the clock source for the RTC CLKSEL may only be updated when CNTEN is 0 The user should ensure that oscillator is enabled before selecting it as a clock source for RTC 00 32 KHz SXOSC 01 128 kHz S...

Страница 1103: ...t Flag The RTCF bit indicates that the RTC counter has reached the counter value matching RTCVAL RTCF is cleared by writing a 1 to RTCF Writing a 0 to RTCF has no effect 1 RTC interrupt 0 No RTC inter...

Страница 1104: ...2 bit value in the RTCC RTCVAL field then the RTCS RTCF interrupt flag bit is set after proper clock synchronization If the RTCC RTCIE interrupt enable bit is set then the RTC interrupt request is gen...

Страница 1105: ...fset When the counter reaches offset count 1 a interrupt and or wakeup request is generated Then the offset value is recalculated and again retriggers a new request when the new value is reached APIVA...

Страница 1106: ...Real Time Clock RTC API MPC5606S Microcontroller Reference Manual Rev 7 1104 Freescale Semiconductor...

Страница 1107: ...r Byte halfword and word addressable ECC protected with single bit correction and double bit detection 33 3 Graphics SRAM The 160 KB of graphics SRAM has no ECC protection and is not powered during st...

Страница 1108: ...he entire 32 bit data width 1 or 2 byte segment the following occurs 1 The ECC mechanism checks the entire 32 bit data bus for errors detecting and either correcting or flagging errors 2 The write dat...

Страница 1109: ...on does not happen Instead synchronous reset SW reset should be used in controlled function without RAM accesses in case initialization procedure is needed without RAM initialization 33 7 Functional d...

Страница 1110: ...ess than 32 bit as discussed in Section 33 6 SRAM ECC mechanism 33 8 Initialization and application information To use the SRAM the ECC must check all bits that require initialization after power on A...

Страница 1111: ...re required while in the case of polyphonic sound only one PWM channel is required Monophonic polyphonic sound can be selected through the signal mono poly_b A 32 bit counter value determines the dura...

Страница 1112: ...ernal signal description Figure 34 2 SGL External signal description 34 2 1 Detailed signal descriptions Table 34 1 Detailed signal descriptions Name Function I O Reset1 1 This is the value that the o...

Страница 1113: ...000 0X0C LOW_PERIOD register R W 0x0000_0000 0X10 SGL_STATUS register R 0x00 Offset 0x00 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R M_P SOUND_CTRL SDCIE CH2_SEL W Reset 0 0 0 0 0 0...

Страница 1114: ...sed to select specific PWM channel to be used by Mux A for sound generation See Table 34 4 for a detailed description Table 34 4 eMIOS channel mapping CHx_SEL eMIOS channel selected CHx_SEL eMIOS chan...

Страница 1115: ...ffset 0x08 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W HIGH_PERIOD...

Страница 1116: ...a tone at the output as shown in signal 3 of Figure 34 8 It is passed through a first order low pass filter to produce signal4 in Figure 34 8 This signal can be fed to the speaker interface Table 34...

Страница 1117: ...SEL which is configured by software The type of sound output monophonic or polyphonic is controlled by MODE_SEL M_P The value of MODE_SEL SOUND_CTRL determines the duration of sound and whether the so...

Страница 1118: ...10 Truth table for MODE_SEL SOUND_CTRL SOUND_ CTRL 2 Periodic Continuous SOUND_ CTRL 1 Begin End SOUND_ CTRL 0 Counter Enable Result X 0 0 No sound generation 0 0 1 Continuous sound is generated until...

Страница 1119: ...d duty cycle and variable frequency Simultaneously mono poly_b is configured such that for monophonic sound generation its value will be one and hence the output from the and gate will be selected i e...

Страница 1120: ...if the MODE_SEL SDCIE bit is 1 If this bit is 0 then the interrupt is disabled The interrupt is generated whenever the SOUND_DURATION counter reaches 0 in cases where sound is being generated for a pr...

Страница 1121: ...ammable timeout 35 1 2 Modes of operation 35 1 2 1 Functional modes 35 1 2 1 1 Dither Function Dither function can be selected or deselected by setting or clearing the MCCTL0 DITH bit This bit influen...

Страница 1122: ...tails please refer to Section 35 4 1 1 3 Half H bridge mode 35 1 2 3 PWM alignment modes Each PWM channel can operate independently in three different alignment modes For details please refer to Secti...

Страница 1123: ...Register MCDC2 Comparator M1C0M M1C0P Duty Register MCDC3 Comparator M1C1M M1C1P Duty Register MCDC4 Comparator M2C0M M2C0P Duty Register MCDC5 Comparator M2C1M M2C1P Duty Register MCDC6 Comparator M...

Страница 1124: ...C0P is driven to a logic high state PWM output on M0C1M results in a positive current flow through coil 1 when M0C1P is driven to a logic high state for details refer to Section 35 4 1 Modes of operat...

Страница 1125: ...ive current flow through coil 0 when M3C0P is driven to a logic high state PWM output on M3C1M results in a positive current flow through coil 1 when M3C1P is driven to a logic high state for details...

Страница 1126: ...oller Channel Control Register 4 MCCC4 RW 8 bit on page 1128 0x15 Motor Controller Channel Control Register 5 MCCC5 RW 8 bit on page 1128 0x16 Motor Controller Channel Control Register 6 MCCC6 RW 8 bi...

Страница 1127: ...1131 0x45 Short circuit Detector Enable Register 1 MCSDE1 RW 8 bit on page 1132 0x46 Short circuit Detector Enable Register 2 MCSDE2 RW 8 bit on page 1132 0x47 Reserved 0x48 Short circuit Detector Int...

Страница 1128: ...ines the prescaler value that sets the motor controller timer counter clock frequency fTC The clock source for the prescaler is the peripheral bus clock fBUS as shown in Figure 35 32 Writes to MCPRE w...

Страница 1129: ...bridge modes In half H bridge mode the PWM output is always active low RECIRC 1 will also invert the effect of the MCDCx SIGN bits refer to Section 35 4 1 3 2 Sign Bit MCDCx SIGN in dual full H bridg...

Страница 1130: ...ment and output mode The number of each register refers directly the PWM channel it controls The relation between channels pin names and register names is shown in Table 35 19 Offset Module Base 0x000...

Страница 1131: ...nCxM pin MnCxP is released 01 Half H bridge mode PWM on pin MnCxP pin MnCxM is released 10 Full H bridge mode 11 Dual full H bridge mode MCAM PWM Channel Alignment Mode MCAM controls the PWM channel s...

Страница 1132: ...not necessarily return the value of the currently active sign duty cycle and dither functionality due to the double buffering scheme Table 35 8 MCDCx field descriptions Field Description SIGN 4 Sign...

Страница 1133: ...ue is used as load value for the short circuit detection counters This value is applied to all 24 short circuit detection blocks Due to synchronization and sampling TOUT must always be larger than 2 s...

Страница 1134: ...tector Enable Each short circuit detector can be enabled or disabled according to the mapping described in Table 35 23 The short circuit detector of a given pin is enabled if the related enable bit is...

Страница 1135: ...hort circuit detector can individually be enabled or disabled according to the mapping described in Table 35 23 The short circuit detector interrupt of a given pin is enabled if the related interrupt...

Страница 1136: ...ally be enabled or disabled according to the mapping described in Table 35 23 The short circuit detector interrupt of a given pin is enabled if the related interrupt enable bit is set to 1 Offset Modu...

Страница 1137: ...f a detected short circuit the corresponding bit according to the mapping in Table 35 23 is set in the short circuit detector interrupt register If this specific interrupt is also enabled in the inter...

Страница 1138: ...ycle register determines the pin where the PWM signal is driven in full H bridge mode While in half H bridge mode the state of the released pin is determined by other modules associated with this pin...

Страница 1139: ...MnC1M drives the PWM signal MnC1P will be an output high or low This results in motor recirculation currents on the high side drivers MCCTL1 RECIRC 0 while the PWM signal is at a logic high level or...

Страница 1140: ...tten 35 4 1 1 2 Full H bridge mode In full H bridge mode MCCCx MCOM 0x2 the PWM channels x and x 1 operate independently The duty cycle working registers are updated whenever a timer counter overflow...

Страница 1141: ...te in full H bridge mode the other as programmed 35 4 1 3 Relationship between Sign Duty Dither RECIRC Period and PWM mode functions 35 4 1 3 1 PWM alignment modes Each PWM channel can be programmed i...

Страница 1142: ...dd periods will be output right aligned PWM operation starts with the even period after the channel has been enabled PWM operation in center aligned mode might start with the odd period if the channel...

Страница 1143: ...le 35 19 outputs a logic high while in dual full H bridge mode In half H bridge mode the state of the MCDCx SIGN 4 bit has no effect The PWM output signal is generated on MnC0P if the PWM channel numb...

Страница 1144: ...IGN 4 bit behavior is inverted if MCCTL1 RECIRC 1 Figure 35 22 Figure 35 23 Figure 35 24 and Figure 35 25 illustrate the effect of the MCCTL1 RECIRC bit in dual full H bridge modes MCCTL1 RECIRC bit m...

Страница 1145: ...nual Rev 7 Freescale Semiconductor 1143 Figure 35 22 PWM Active Phase MCCTL1 RECIRC 0 MCDCx SIGN 4 0 Figure 35 23 PWM Passive Phase MCCTL1 RECIRC 0 MCDCx SIGN 4 0 VDDM VSSM MnC0P MnC0M Static 0 PWM 1...

Страница 1146: ...SIGN 4 0 Figure 35 25 PWM Passive Phase MCCTL1 RECIRC 1 MCDCx SIGN 4 0 35 4 1 3 4 Relationship between MCCTL1 RECIRC bit MCDCx SIGN 4 bit MCCCx MCOM bits PWM state and output transistors Please refer...

Страница 1147: ...L1 RECIRC MCDCx SIGN 4 T1 T2 T3 T4 MnC yM MnC yP Off Don t care Don t care Don t care Half H Bridge 0x0 Active Don t care Don t care OFF ON 0 Half H Bridge 0x0 Passive Don t care Don t care ON OFF 1 H...

Страница 1148: ...y cycle value MCDCx DUTY When a match output compare between motor controller timer counter and MCDCx DUTY occurs the PWM output will toggle to a logic high level and will remain at a logic high level...

Страница 1149: ...lue defined by MCPER PER 10 1 1 After the motor controller timer counter resets to 0x000 the PWM output will return to a logic low level This process will repeat every number of counts of the motor co...

Страница 1150: ...C 0 Figure 35 31 PWM Output MCCTL0 DITH 1 MCCCx MCAM 0x3 MCDCx DUTY 31 MCPER PER 200 MCCTL1 RECIRC 0 PWM Output 1 Period 100 Counts Motor Controller Timer Counter Motor Controller Timer Counter Clock...

Страница 1151: ...rce is selected Figure 35 32 Motor Controller Counter Clock Selection The peripheral bus clock is the source for the motor controller counter prescaler The motor controller counter clock rate fTC is s...

Страница 1152: ...e between 0 1 2 or 3 motor controller timer counter clock cycles NOTE A PWM channel gets disabled at the next timer counter overflow without notice of the switching delay 35 4 5 Operation in SMC stop...

Страница 1153: ...SDEN 4 MCSDIEN2 SDIE 4 MCSDI2 SDIF 4 19 2 M1C0M MCSDE2 SDEN 3 MCSDIEN2 SDIE 3 MCSDI2 SDIF 3 18 0 M0C0M MCSDE2 SDEN 2 MCSDIEN2 SDIE 2 MCSDI2 SDIF 2 17 11 M5C1M MCSDE2 SDEN 1 MCSDIEN2 SDIE 1 MCSDI2 SDIF...

Страница 1154: ...and is reset to the timeout value MCSDTO TOUT in order to be ready for the next transaction PWM Generator PWM FB Timer TOUT MCSDEn SDEN sd MCSDIn SDIF sd Motor Pin i DFF DFF AND Synchronizer PWM FB_s...

Страница 1155: ...om the previous state If the short circuit detector should restart with defined state counter value MCSDTO TOUT than the related detector shall be disabled and enabled again This will reload the count...

Страница 1156: ...between FB at pin and the internal PWM signal PWM Signal from motor controller FB at pin This is the signal directly after the input driver of the pad s ignal FB_Sample Pad signal after sampling and s...

Страница 1157: ...MCTOIE bit to 0 or to write a one to the MCCTL0 MCTOIF bit 24 Interrupts for the short circuit detection one for each PWM pin Whenever a short circuit is detected on one PWM pin and the short circuit...

Страница 1158: ...controller Reference Manual Rev 7 1156 Freescale Semiconductor Figure 35 37 SMC Interrupt Generation MCSDI0 MCSDI1 MCSDI2 MCTOIF MCSDIE0 MCSDIE1 MCSDIE2 MCTOIE 25 bits 25 bits Bitwise AND OR of all in...

Страница 1159: ...f the scale Basis of the movement detection is to drive one of the coils and to integrate the back EMF electromotive force induced in the other coil This back EMF is present only if the SM is rotating...

Страница 1160: ...ection 36 4 1 Main building blocks of the SSD Analog Block relates to Section 36 4 1 1 Analog block Analog Wrapper and Port Control relates to Section 36 4 1 2 Analog Wrapper Port Control Analog Block...

Страница 1161: ...BIS Separate down counter initialization values and divider factors Separate interrupt flags and interrupt enable bits Separate coil drive enable bits Polarity switching to cancel DC offset errors pr...

Страница 1162: ...hat all registers are 16 bits in width There is no access on byte level 36 3 1 Memory map Table 36 2 lists the registers of the SSD block Table 36 1 Signal properties Name Port Coil Coil Node I O Rese...

Страница 1163: ...te for the electromagnetic field in the SM 01 Select 90 angle north pole state for the electromagnetic field in the SM 10 Select 180 angle west pole state for the electromagnetic field in the SM 11 Se...

Страница 1164: ...Up Setting this bit enables the analog block of the SSD and enables the clocking of the port control logic of the digital part 1 Analog block of the SSD is enabled 0 Analog block of the SSD is not en...

Страница 1165: ...0 The ITGIF flag will not trigger an interrupt on the ips_int output 0 ACOVIE Accumulator Interrupt Enable 1 A module interrupt will occur if the ACOVIF bit is set 0 The ACOVIF flag will not trigger a...

Страница 1166: ...0 0 0 0 Figure 36 6 SSD Blanking Counter Load Register BLNCNTLD Table 36 7 BLNCNTLD Register field description Field Description 15 0 BLNCNTLD Blanking Count Load value This register is programmed wit...

Страница 1167: ...Select The frequency for updating the down counter in the integration phase of the next BISs is derived from the bus clock according to the formula down counter clock bus clock 8 2ITGDIV According to...

Страница 1168: ...f the analog block of the SSD block is given in Figure 36 9 below Additionally the most important sub blocks of the digital part which are connected to the analog blocks are shown in order to clarify...

Страница 1169: ...utput value provided to the digital part is used to increment or decrement the ITGACC register Sine Coil Cosine Coil Bus VDDM COSP COSM T1 T2 T3 VSSM VDDM T4 VSSM S1 S3 S2 S4 VDDM SINP SINM T5 T6 T7 V...

Страница 1170: ...nally the direction of the current flow is selected with these bits For clockwise direction of the SM movement the value must be decremented and for counter clockwise movement it must be incremented w...

Страница 1171: ...0 0 0 OFF OFF OFF OFF ON OFF ON OFF Blanking with no drive RCIR bit determines supply voltage for recirculation 00 0 0 1 OFF OFF OFF OFF OFF ON OFF ON 01 0 0 0 ON OFF ON OFF OFF OFF OFF OFF 01 0 0 1...

Страница 1172: ...Access size is 32 bits the SSD block supports 16 and 32 bit accesses Table 36 11 Generation of the Resulting DCOIL BLNST BLNDCL ITGST ITGDCL Resulting DCOIL Remarks 0 x 0 0 0 No running BIS ITGDCL det...

Страница 1173: ...gister is initialized with 0x0000 The integration phase of the BIS is executed the ITGDCL bit is used to determine whether one of the coils is driven during the integration phase The modulator of the...

Страница 1174: ...s sampled periodically and the content of the accumulator incremented or decremented Therefore the ITGACC register in fact counts the imbalance between 1 and 0 output samples from the analog block The...

Страница 1175: ...n accumulator ITGACC register Initially it is applied without change to the integration accumulator As a result the switch conditions in the analog circuitry change the direction of the voltage repres...

Страница 1176: ...f SSD measurement is given in Figure 36 11 below the numbers denoted at each step belong to the detailed explanations given in Section 36 4 2 2 Details of the SSD Measurement The two phases of the BIS...

Страница 1177: ...M step is required must be made by the controlling CPU depending from the measurement result All control bits are assumed to have their inactive reset values prior to entering the SSD measurement flow...

Страница 1178: ...mented or incremented wrapping from 2 b11 to 2 b00 or vice versa If the BLNDCL bit is set this step marks the start of the SM movement During blanking both pins of the non driven coil are connected ei...

Страница 1179: ...tion with No Drive If the ITGDCL bit is switched off the driving coil of the SM is not powered during the integration phase the SM will not move Only the modulator output is integrated with the refere...

Страница 1180: ...lock by setting the SDCPU bit 36 6 Application information This is additional information intended for use by the customer 36 6 1 Current flow examples Figure 36 12 below shows the current flow for a...

Страница 1181: ...nd the cosine coil is recirculated against VSSM Figure 36 14 Current flow for Blanking STEP 1 BLNDCL 1 RCIR 1 In Figure 36 15 below it is shown that for the next step STEP 2 the cosine coil is driven...

Страница 1182: ...the analog supply voltages because it is the integration phase of the current BIS Figure 36 16 Current flow for Integration STEP 3 ITGDCL 1 36 6 2 Setting of the PRESCALE Register 36 6 2 1 Timing Reso...

Страница 1183: ...is always an integer multiple or divider of the ITGACC register update depending which divider factor is greater than the other one If the offset cancellation is used the measurement polarity in the a...

Страница 1184: ...ne of the SM coils is driven and the SM retains its position when the SSD block gets pad control Vice versa the STEP and ITGDCL setting at the end of the last BIS where the gauge stall was detected al...

Страница 1185: ...0x0000 When the corresponding BIS is executed this phase is simply skipped Note that in this case the BLNIF bit will be important for the user because its assertion marks the end of the blanking phase...

Страница 1186: ...Stepper Stall Detect SSD MPC5606S Microcontroller Reference Manual Rev 7 1184 Freescale Semiconductor...

Страница 1187: ...configuration ports general purpose input and output GPIO signals and external interrupts with trigger event configuration Figure 37 1 is a block diagram of the SIUL and its interfaces to other system...

Страница 1188: ...block diagram 1 Up to 105 I O pins in the 144 pin packages up to 133 I O pins in the 176 and 208 pin packages IPS BUS Data Pad Input IO Interrupt Interrupt Controller IPS Master Configuration Glitch...

Страница 1189: ...centralized general purpose I O for an MCU that multiplexes GPIO with other signals at the I O pads These other signals or alternate functions will normally be the peripherals functions The internal...

Страница 1190: ...the SIU_IREER or the SIU_IFEER register 37 5 Memory map and register description This section provides a detailed description of all registers accessible in the SIUL module 37 5 1 SIUL memory map Tab...

Страница 1191: ...on for Multiplexed Inputs 32 bit on page 1198 Base 0x052C 0x05FF Reserved Base 0x0600 Base 0x0684 GPDO0_3 GPDO132_1351 GPIO Pad Data Output Register 32 bit on page 1202 Base 0x0688 07FF Reserved Base...

Страница 1192: ...egisters Under Protection for details 37 5 3 Register description This section describes in address order all the SIUL registers Each description includes a standard register diagram Details of regist...

Страница 1193: ...IDR1 Table 37 3 MIDR1 field descriptions Field Description PARTNUM 15 0 MCU Part Number Device part number of the MCU 0101_0110_0000_0001 128K 0101_0110_0000_0010 256K 0101_0110_0000_0011 320 384K 010...

Страница 1194: ...4 MIDR2 field descriptions Field Description SF Manufacturer 0 Freescale Semiconductor 1 Reserved FLASH_SIZE_1 Coarse granularity for Flash memory size Needs to be added to the memory size indicated b...

Страница 1195: ...Register ISR Table 37 5 ISR field descriptions Field Description EIF x External Interrupt Status Flag x This flag can be cleared only by writing a 1 Writing a 0 has no effect If enabled IRER x EIF x...

Страница 1196: ...18 19 20 21 22 23 24 25 26 27 28 29 30 31 R IREE 13 0 1 1 IREE 11 0 is valid in the 144 pin LQFP W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 37 7 Interrupt Rising Ed...

Страница 1197: ...depending on the number of alternate functions actually mapped on the pad Address Base 0x0030 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30...

Страница 1198: ...Analog input path switch can be enabled by the ADC PA 1 0 Pad Output Assignment This field is used to select the function that is allowed to drive the output of a multiplexed pad 00 Alternative Mode 0...

Страница 1199: ...ng low power modes WPE Weak Pullup Pulldown Enable This bit controls whether the weak pullup pulldown devices are enabled disabled for the pad connected to this signal Note When a pin is configured as...

Страница 1200: ...0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 PADSEL2 0 0 0 0 PADSEL3 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 37 12 Pad Selection for Multiplexed Inputs Register PS...

Страница 1201: ...U_PDI 13 0 PCR 122 1 PCR 126 PSMI 14 0x50E DSPI1_SS 0 PCR 43 1 PCR 79 PSMI 15 0x50F EMIOS0_CH8 0 PCR 69 1 PCR 91 2 PCR 98 PSMI 16 0x510 EMIOS0_CH9 0 PCR 15 1 PCR 68 2 PCR 75 PSMI 17 0x511 EMIOS0_CH10...

Страница 1202: ...R 70 2 PCR 111 PSMI 30 0x51E EMIOS0_CH23 0 PCR 26 1 PCR 98 PSMI 31 0x51F EMIOS1_CH16 0 PCR 53 1 PCR 82 2 PCR 103 PSMI 32 0x520 EMIOS1_CH17 0 PCR 52 1 PCR 90 2 PCR 117 PSMI 33 0x521 EMIOS1_CH18 0 PCR 9...

Страница 1203: ...PSMI 41 0x529 LINFLEX_RXD_1 0 PCR 28 1 PCR 78 PSMI 42 0x52A EVTI 0 PCR 126 1 EVTI 1 Connecting a peripheral input to a pad requires assigning both the PSMI value for the peripheral input and the pad a...

Страница 1204: ...d to set or clear the logic value on their associated pads Each word contains four registers The word beginning at Base 0x0600 contains GPDI0 GPDI3 the word beginning at Base 0x0604 contains GPDI3 GPD...

Страница 1205: ...set 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 37 14 Port GPIO Pad Data Input register 0 3 GPDI0_3 Table 37 14 GPDI field descriptions Field Description PDI x Pad Data In This bit stores the value of the...

Страница 1206: ...PDO 32 Table 37 15 PGPDO0_4 field descriptions Field Description PPDO x Parallel Pad Data Out Write or read the data register that stores the value to be driven on the pad in output mode Accesses to t...

Страница 1207: ...0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R PPDI x 1 15 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 37 16 Parallel GPIO Pad Data In Register PGPDI0 Table 37 16 PGPDI fiel...

Страница 1208: ...21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W MPPDO x 15 0 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 37 17 Masked Parallel GPIO Pad Data Out Register MPGPDO0 Table 37 17 MPGP...

Страница 1209: ...17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 MAXCNTx 3 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 37 18 Interrupt Filter Maximum Counter Registers IFMC0 IFMC15 Table 37...

Страница 1210: ...ut enable Slew rate control Pull control Pad assignment Control of analog path switches Safe mode behavior configuration 37 6 3 General purpose input and output pads GPIO The SIUL allows each pad to b...

Страница 1211: ...is configured to use one of its alternate functions the data input value reflect the respective value of the pad If a write operation is performed to the data output register for a pad configured as a...

Страница 1212: ...for the pad is enabled PCR IBE 1 The active EIRQ edge is controlled through the configuration of the registers IREER and IFEER Each external interrupt supports an individual flag which is held in the...

Страница 1213: ...System Integration Unit Lite SIUL MPC5606S Microcontroller Reference Manual Rev 7 Freescale Semiconductor 1211...

Страница 1214: ...System Integration Unit Lite SIUL MPC5606S Microcontroller Reference Manual Rev 7 1212 Freescale Semiconductor...

Страница 1215: ...te Standby power domain the System Status block is part of that domain Figure 38 1 System Status and Configuration Module block diagram 38 1 2 Features The SSCM includes these distinctive features Sys...

Страница 1216: ...0002 but performing a 16 bit access to Base 0x0003 is illegal 38 2 2 Register description The following memory mapped registers are available in the SSCM Those bits that are shaded out are reserved fo...

Страница 1217: ...igned to 32 bit addresses i e 0x0 0x4 0x8 or 0xC READ Allowed Allowed Allowed WRITE Not Allowed Not Allowed Not Allowed Table 38 3 STATUS field descriptions Field Description 4 NXEN Nexus enabled PUB...

Страница 1218: ...memory map The Flash may not be accessible due to security limitations or because there is no Flash in the system 0 Code Flash is not accessible 1 Code Flash is accessible DVLD Data Flash Valid This b...

Страница 1219: ...en developing application code 0 Illegal accesses to peripherals do not produce a Prefetch or Data Abort exception Transfers to Peripheral Bus resources may be aborted even before they reach the Perip...

Страница 1220: ...rved 4 STATUS 4 STATUS 12 MEMCONFIG 4 MEMCONFIG 12 Reserved Reserved Reserved 5 STATUS 5 STATUS 13 MEMCONFIG 5 MEMCONFIG 13 Reserved Reserved Reserved 6 STATUS 6 STATUS 14 MEMCONFIG 6 MEMCONFIG 14 Res...

Страница 1221: ...nd for debug of the system Address 0x0010 Access Read Write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W PWD_LO 0 15 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 2...

Страница 1222: ...le SSCM MPC5606S Microcontroller Reference Manual Rev 7 1220 Freescale Semiconductor 38 4 Initialization application information 38 4 1 Reset The reset state of each individual bit is shown within the...

Страница 1223: ...endent interrupt source for each channel Counter can be stopped in debug mode 39 1 3 Modes of operation The STM supports two device modes of operation normal and debug When the STM is enabled in norma...

Страница 1224: ...er 32 R W on page 1224 0x0014 STM_CIR0 STM Channel 0 Interrupt Register 32 R W on page 1224 0x0018 STM_CMP0 STM Channel 0 Compare Register 32 R W on page 1225 0x001C Reserved 0x0020 STM_CCR1 STM Chann...

Страница 1225: ...aler Selects the clock divide value for the prescaler 1 256 0x00 Divide system clock by 1 0x01 Divide system clock by 2 0xFF Divide system clock by 256 FRZ Freeze Allows the timer counter to be stoppe...

Страница 1226: ...1 12 13 14 15 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN W Reset 0 0 0 0 0 0 0 0 0 0...

Страница 1227: ...M_CR FRZ bit is set the counter is stopped in debug mode otherwise it continues to run in debug mode The counter rolls over at 0xFFFF_FFFF to 0x0000_0000 with no restrictions at this boundary The STM...

Страница 1228: ...System Timer Module STM MPC5606S Microcontroller Reference Manual Rev 7 1226 Freescale Semiconductor NOTE The STM counter does not advance when the system clock is stopped...

Страница 1229: ...regulator HPREG requiring an external NPN ballast transistor Low power regulator LPREG Ultra low power regulator ULPREG The HPREG and LPREG regulators are switched off in Standby mode to save power c...

Страница 1230: ...v 7 1228 Freescale Semiconductor 40 2 1 Block diagram Figure 40 1 Voltage regulator diagram 40 2 2 External signals Table 40 1 provides an overview of the voltage regulator external signals CORE MLVDD...

Страница 1231: ...1 Voltage regulator external signals Name Type Voltage Description VDDR Supply 3 0 V 5 5 V Power Supply for the voltage regulators VSSR Ground Ground supply for digital core and voltage regulators VRC...

Страница 1232: ...anaged by MC_ME 40 4 3 Ultra Low power Regulator ULPREG The ULPREG generates power for the standby domain as well as a part of the main domain The control circuit of ULPREG can be used to disable the...

Страница 1233: ...ve the minimum value of VPORUP refer to the MPC5606S Microcontroller Data Sheet for this value It will be released only after the Vdd supply goes above VPORH refer to the MPC5606S Microcontroller Data...

Страница 1234: ...tions are available simultaneously Refer to Chapter 3 Signal Description Supply pins Port pins Stepper Motor Bank Stepper Motors 1 0 eMIOS Stepper Motors 3 2 eMIOS Stepper Motors 5 4 eMIOS VDDMA2 VSSM...

Страница 1235: ...supplies that are separated from each other by the use of power switches These R Analog Bank 0 Stepper Motor Bank Digital Bank 1 Digital Bank 0 Digital Bank 2 VREG 4 16 MHz FMPLL FXOSC VDDR VRC_CTRL V...

Страница 1236: ...hence able to switch off power to certain regions of the device to avoid even leakage current consumption in logic supplied by the corresponding power supply This device employs three primary power do...

Страница 1237: ...HPVDD ULPVDD LPVDD SW1 128 kHz RC MC_RGM 16 MHz RC VRC_CTRL HV POR1HV POR2HV nbypass HPPD LPPD VREG API CAN sampler WKPU CFLASH 160K RC Dig Wakeup Pads SIUL Option Reset e200z0h platform PA0 MC_CGM M...

Страница 1238: ...Voltage Regulators and Power Supplies MPC5606S Microcontroller Reference Manual Rev 7 1236 Freescale Semiconductor...

Страница 1239: ...the Wakeup Unit and its interfaces to other system components The wakeup lines are mapped to the interrupt vectors as shown in Table 41 1 Figure 41 1 Wakeup Unit block diagram 1 Up to 19 external sou...

Страница 1240: ...tor Wakeup Number Function Package Port 1 2 3 Special 144 176 208 0 WKPU0 PA0 DCU_R0 eMIOSA22 SOUND FP23 x x x WKPU1 PB1 CANRX_0 PDI0 x x x WKPU2 PB3 RXD_0 x x x WKPU3 PB4 SCK_1 MA0 x x x WKPU4 PB9 SC...

Страница 1241: ...ke up pins should be correctly terminated to ensure minimal current consumption Any unused Wake up signal input should be terminated by using an external pullup or pulldown or by internal pullup enabl...

Страница 1242: ...F 5 WISR 26 41 4 2 1 NMI Status Flag Register NSR This register holds the non maskable interrupt status flags 0x0020 0x0027 Reserved 0x0028 Wakeup Interrupt Rising Edge Event Enable Register WIREER 32...

Страница 1243: ...ed on NMI input 1 An overrun has occurred on NMI input Address Base 0x0008 Access User read write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R NLO CK NDSS NWR E 0 NRE E NFE E NFE 0 0 0 0 0 0 0 0 W Reset 0...

Страница 1244: ...ent is disabled 0 Falling edge event is disabled 1 Falling edge event is enabled 7 NFE NMI Filter Enable Enable analog glitch filter on the NMI pad input 0 Filter is disabled 1 Filter is enabled Addre...

Страница 1245: ...7 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 EIRE 20 0 1 1 Not all bits are available in the 144 pin package W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 41 5 Interrupt Requ...

Страница 1246: ...ilable in the 144 pin package W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 41 7 Wakeup Interrupt Rising Edge Event Enable Register WIREER Table 41 8 WIREER field desc...

Страница 1247: ...6 27 28 29 30 31 R 0 0 0 0 0 0 0 0 0 0 0 IFE 20 0 1 1 Not all bits are available in the 144 pin package W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 41 9 Wakeup Inter...

Страница 1248: ...rocess itself Figure 41 11 NMI Pad Diagram 41 5 2 1 NMI Management The NMI can be enabled or disabled using the single NCR register laid out to contain all configuration bits for an NMI in a single by...

Страница 1249: ...TE The overrun flag is cleared by writing a 1 to the appropriate overrun bit in the NSR register If the status bit is cleared and the overrun bit is still set the pending interrupt will not be cleared...

Страница 1250: ...can be configured by the user to recognize external interrupts with an active rising edge an active falling edge or both edges being active NOTE Writing a 0 to both IREE x and IFEE x disables the exte...

Страница 1251: ...chip wakeups with the external ones to generate a single wakeup to the system 41 5 4 1 On Chip Wakeup Management In order to allow software to determine the wakeup source at one location on chip wake...

Страница 1252: ...Wakeup Unit WKPU MPC5606S Microcontroller Reference Manual Rev 7 1250 Freescale Semiconductor...

Страница 1253: ...lash BIU1 32 C3F88000 020 bits 0 31 Code Flash BIU2 32 C3F88000 024 bits 0 31 Data Flash 1 registers to protect Data Flash MCR 32 C3F8C000 000 bits 0 31 SIU lite 64 registers to protect SIUL IRER 32 C...

Страница 1254: ...090 bits 0 15 SIUL PCR41 16 C3F90000 092 bits 0 15 SIUL PCR42 16 C3F90000 094 bits 0 15 SIUL PCR43 16 C3F90000 096 bits 0 15 SIUL PCR44 16 C3F90000 098 bits 0 15 SIUL PCR45 16 C3F90000 09A bits 0 15...

Страница 1255: ...00 02C bits 0 31 MC_ME ME_RUN0_MC 32 C3FDC000 030 bits 0 31 MC_ME ME_RUN1_MC 32 C3FDC000 034 bits 0 31 MC_ME ME_RUN2_MC 32 C3FDC000 038 bits 0 31 MC_ME ME_RUN3_MC 32 C3FDC000 03C bits 0 31 MC_ME ME_HA...

Страница 1256: ...63 32 C3FDC000 0FC bits 0 31 MC_ME ME_PCTL 68 71 32 C3FDC000 104 bits 0 31 MC_ME ME_PCTL 72 75 32 C3FDC000 108 bits 0 31 MC_ME ME_PCTL 88 91 32 C3FDC000 118 bits 0 31 MC_ME ME_PCTL 92 95 32 C3FDC000 1...

Страница 1257: ...0 15 MC_RGM RGM_FESS 16 C3FE4000 018 bits 0 15 MC_RGM RGM_STDBY 16 C3FE4000 01A bits 0 15 MC_RGM RGM_FBRE 16 C3FE4000 01C bits 0 15 MC Power Control Unit 1 registers to protect MC_PCU PCONF2 32 C3FE80...

Страница 1258: ...Registers Under Protection MPC5606S Microcontroller Reference Manual Rev 7 1256 Freescale Semiconductor...

Страница 1259: ...0xFFF9_4000 on page 1305 ECSM 0xFFF4_0000 on page 1299 eMIOS 0 0xC3FA_0000 on page 1268 eMIOS 1 0xC3FA_4000 on page 1275 FlexCan 0 CAN0 0xFFFC_0000 on page 1306 FlexCan 1 CAN1 0xFFFC_4000 on page 1310...

Страница 1260: ...ailed register map Register description Register Name Used Size Address Program FLASH 0 Configuration Section 17 4 3 Memory map and register definition 0xC3F8_8000 Module Configuration Register CFLASH...

Страница 1261: ...Block Locking Register DFLASH_SLL 32 bit Base 0x000C Low Mid Address Space Block Select Register DFLASH_LMS 32 bit Base 0x0010 High Address Space Block Select Register DFLASH_HBS 32 bit Base 0x0014 A...

Страница 1262: ...nfiguration Register 7 PCR7 16 bit Base 0x004E Pad Configuration Register 8 PCR8 16 bit Base 0x0050 Pad Configuration Register 9 PCR9 16 bit Base 0x0052 Pad Configuration Register 10 PCR10 16 bit Base...

Страница 1263: ...ation Register 38 PCR38 16 bit Base 0x008C Pad Configuration Register 39 PCR39 16 bit Base 0x008E Pad Configuration Register 40 PCR40 16 bit Base 0x0090 Pad Configuration Register 41 PCR41 16 bit Base...

Страница 1264: ...ation Register 70 PCR70 16 bit Base 0x00CC Pad Configuration Register 71 PCR71 16 bit Base 0x00CE Pad Configuration Register 72 PCR72 16 bit Base 0x00D0 Pad Configuration Register 73 PCR73 16 bit Base...

Страница 1265: ...02 PCR102 16 bit Base 0x010C Pad Configuration Register 103 PCR103 16 bit Base 0x010E Pad Configuration Register 104 PCR104 16 bit Base 0x0110 Pad Configuration Register 105 PCR105 16 bit Base 0x0112...

Страница 1266: ...ed Inputs PSMI0_3 32 bit Base 0x0500 Pad Selection for Multiplexed Inputs PSMI4_7 32 bit Base 0x0504 Pad Selection for Multiplexed Inputs PSMI8_11 32 bit Base 0x0508 Pad Selection for Multiplexed Inpu...

Страница 1267: ...84_87 32 bit Base 0x0654 GPIO Pad Data Output Register GPDO88_91 32 bit Base 0x0658 GPIO Pad Data Output Register GPDO92_95 32 bit Base 0x065C GPIO Pad Data Output Register GPDO96_99 32 bit Base 0x066...

Страница 1268: ...I80_83 32 bit Base 0x0850 GPIO Pad Data Input Register GPDI84_87 32 bit Base 0x0854 GPIO Pad Data Input Register GPDI88_91 32 bit Base 0x0858 GPIO Pad Data Input Register GPDI92_95 32 bit Base 0x085C...

Страница 1269: ...ase 0x1000 Interrupt Filter Maximum Counter Register IFMC1 32 bit Base 0x1004 Interrupt Filter Maximum Counter Register IFMC2 32 bit Base 0x1008 Interrupt Filter Maximum Counter Register IFMC3 32 bit...

Страница 1270: ...Register WKPU_WIFEER 32 bit Base 0x002C Wakeup Interrupt Filter Enable Register WKPU_WIFER 32 bit Base 0x0030 Wakeup Interrupt Pullup Enable Register WKPU_WIPUER 32 bit Base 0x0034 Reserved Base 0x003...

Страница 1271: ...bit Base 0x0070 Reserved Base 0x0074 0x007F eMIOS0 UC3 A Register EMIOS0_UC3_A 32 bit Base 0x0080 eMIOS0 UC3 B Register EMIOS0_UC3_B 32 bit Base 0x0084 Reserved Base 0x0088 0x008B eMIOS0 UC3 Control R...

Страница 1272: ...32 bit Base 0x0100 eMIOS0 UC7 B Register EMIOS0_UC7_B 32 bit Base 0x0104 Reserved Base 0x0108 0x010B eMIOS0 UC7 Control Register EMIOS0_UC7_SC 32 bit Base 0x010C eMIOS0 UC7 Status Register EMIOS0_UC7_...

Страница 1273: ...0184 Reserved Base 0x0188 0x018B eMIOS0 UC11 Control Register EMIOS0_UC11_SC 32 bit Base 0x018C eMIOS0 UC11 Status Register EMIOS0_UC11_SS 32 bit Base 0x0190 Reserved Base 0x0194 0x019F eMIOS0 UC12 A...

Страница 1274: ...Register EMIOS0_UC15_SS 32 bit Base 0x0210 Reserved Base 0x0214 0x021F eMIOS0 UC16 A Register EMIOS0_UC16_A 32 bit Base 0x0220 eMIOS0 UC16 B Register EMIOS0_UC16_B 32 bit Base 0x0224 eMIOS0 UC16 CNT...

Страница 1275: ...0x0294 0x029F eMIOS0 UC20 A Register EMIOS0_UC20_A 32 bit Base 0x02A0 eMIOS0 UC20 B Register EMIOS0_UC20_B 32 bit Base 0x02A4 Reserved Base 0x02A8 0x02AB eMIOS0 UC20 Control Register EMIOS0_UC20_SC 3...

Страница 1276: ...r EMIOS0_UC24_B 32 bit Base 0x0324 eMIOS0 UC24 CNT EMIOS0_UC24_CNT 32 bit Base 0x0328 eMIOS0 UC24 Control Register EMIOS0_UC24_SC 32 bit Base 0x032C eMIOS0 UC24 Status Register EMIOS0_UC24_SS 32 bit B...

Страница 1277: ...1 UC0 B Register eMIOS1_UC0_B 32 bit Base 0x0024 eMIOS1 UC0 CNT eMIOS1_UC0_CNT 32 bit Base 0x0028 eMIOS1 UC0 Control Register eMIOS1_UC0_SC 32 bit Base 0x002C eMIOS1 UC0 Status Register eMIOS1_UC0_SS...

Страница 1278: ...ster eMIOS1_UC4_SC 32 bit Base 0x00AC eMIOS1 UC4 Status Register eMIOS1_UC4_SS 32 bit Base 0x00B0 Reserved Base 0x00B4 0x00BF eMIOS1 UC5 A Register eMIOS1_UC5_A 32 bit Base 0x00C0 eMIOS1 UC5 B Registe...

Страница 1279: ...eMIOS1_UC8_SS 32 bit Base 0x0130 Reserved Base 0x0134 0x013F eMIOS1 UC9 A Register eMIOS1_UC9_A 32 bit Base 0x0140 eMIOS1 UC9 B Register eMIOS1_UC9_B 32 bit Base 0x0144 Reserved Base 0x0148 0x014B eM...

Страница 1280: ...Register eMIOS1_UC13_A 32 bit Base 0x01C0 eMIOS1 UC13 B Register eMIOS1_UC13_B 32 bit Base 0x01C4 Reserved Base 0x01C8 0x01CB eMIOS1 UC13 Control Register eMIOS1_UC13_SC 32 bit Base 0x01CC eMIOS1 UC13...

Страница 1281: ...eMIOS1_UC17_B 32 bit Base 0x0244 Reserved Base 0x0248 0x024B eMIOS1 UC17 Control Register eMIOS1_UC17_SC 32 bit Base 0x024C eMIOS1 UC17 Status Register eMIOS1_UC17_SS 32 bit Base 0x0250 Reserved Base...

Страница 1282: ...1_SC 32 bit Base 0x02CC eMIOS1 UC21 Status Register eMIOS1_UC21_SS 32 bit Base 0x02D0 Reserved Base 0x02D4 0x02DF eMIOS1 UC22 A Register eMIOS1_UC22_A 32 bit Base 0x02E0 eMIOS1 UC22 B Register eMIOS1_...

Страница 1283: ...eserved Base 0x0354 0x035F eMIOS1 UC26 A Register eMIOS1_UC26_A 32 bit Base 0x0360 Reserved Base 0x0364 0x036B eMIOS1 UC26 Control Register eMIOS1_UC26_SC 32 bit Base 0x036C eMIOS1 UC26 Status Registe...

Страница 1284: ...Mode Transition status ME_IMTS 32 bit Base 0x0014 Reserved Base 0x0018 0x001F Reset Mode Configuration ME_RESET_MC 32 bit Base 0x0020 Test Mode Configuration ME_TEST_MC 32 bit Base 0x0024 Safe Mode C...

Страница 1285: ...guration Registers ME_LP_PC0 32 bit Base 0x00A0 Low Power Peripheral Configuration Registers ME_LP_PC1 32 bit Base 0x00A4 Low Power Peripheral Configuration Registers ME_LP_PC2 32 bit Base 0x00A8 Low...

Страница 1286: ...Base 0x00F2 Peripheral Control Registers ME_PCTL51 8 bit Base 0x00F3 Reserved Base 0x00F4 0x00F8 Peripheral Control Registers ME_PCTL57 8 bit Base 0x00F9 Reserved Base 0x00FA 0x00FB Peripheral Contro...

Страница 1287: ...rface Section 8 7 3 Register descriptionn 0xC3FE_0080 Low Power RC Control Register LPRC_CTL 32 bit Base 0x0000 Reserved Base 0x0004 0x009F PLLD0 Section 8 9 5 Register description 0xC3FE_00A0 Control...

Страница 1288: ...Base 0x0000 Destructive Event Status RGM_DES 16 bit Base 0x0002 Functional Event Reset Disable RGM_FERD 16 bit Base 0x0004 Destructive Event Reset Disable RGM_DERD 16 bit Base 0x0006 Reserved Base 0x...

Страница 1289: ...r 0 CVAL0 32 bit Base 0x0104 Timer Control Register 0 TCTRL0 32 bit Base 0x0108 Timer Flag Register 0 TFLG0 32 bit Base 0x010C Timer Load Value Register 1 LDVAL1 32 bit Base 0x0110 Current Timer Value...

Страница 1290: ...EOCFR1 32 bit Base 0x018 Channel Pending Register CEOCFR2 32 bit Base 0x01C Interrupt Mask Register IMR 32 bit Base 0x020 Reserved Base 0x024 Channel Interrupt Mask Register CIMR1 32 bit Base 0x028 Ch...

Страница 1291: ...x0BC Reserved Base 0x0C0 Decode Signals Delay Register DSDR 32 bit Base 0x0C4 Power down Exit Delay Register PDEDR 32 bit Base 0x0C8 Reserved Base 0x0CC 0x17C Channel 32 Data Register CDR32 32 bit Bas...

Страница 1292: ...description 0xFFE3_0000 I2C Bus Address Register IBAD 8 bit Base 0x0000 I2C Bus Frequency Divider Register IBFD 8 bit Base 0x0001 I2C Bus Control Register IBCR 8 bit Base 0x0002 I2C Bus Status Regist...

Страница 1293: ...ter IBCR 8 bit Base 0x0002 I2C Bus Status Register IBSR 8 bit Base 0x0003 I2C Bus Data I O Register IBDR 8 bit Base 0x0004 I2C Bus Interrupt Config Register IBIC 8 bit Base 0x0005 Reserved Base 0x0006...

Страница 1294: ...16 bit Base 0x0028 Reserved Base 0x002A 0x002B LIN Checksum Field Register LINCFR 16 bit Base 0x002C Reserved Base 0x002E 0x002F LIN Control Register 2 LINCR2 16 bit Base 0x0030 Reserved Base 0x0032...

Страница 1295: ...0x0058 Reserved Base 0x005A 0x005B Identifier Filter Control Register IFCR4 16 bit Base 0x005C Reserved Base 0x005E 0x005F Identifier Filter Control Register IFCR5 16 bit Base 0x0060 Reserved Base 0x0...

Страница 1296: ...egister IFCR15 16 bit Base 0x0088 Reserved Base 0x009A 0x3FFF LINFlex 1 Section 23 7 Memory map and registers description 0xFFE4_4000 LIN Control Register LINCR1 16 bit Base 0x0000 Reserved Base 0x000...

Страница 1297: ...sum Field Register LINCFR 16 bit Base 0x002C Reserved Base 0x002E 0x002F LIN Control Register 2 LINCR2 16 bit Base 0x0030 Reserved Base 0x0032 0x0033 Buffer Identifier Register BIDR 16 bit Base 0x0034...

Страница 1298: ...rror Detail Register Slave Port 0 MPU_EDR0 32 bit Base 0x0014 MPU Error Address Register Slave Port 1 MPU_EAR1 32 bit Base 0x0018 MPU Error Detail Register Slave Port 1 MPU_EDR1 32 bit Base 0x001C MPU...

Страница 1299: ...0x0500 0x07FF MPU RGD Alternate Access Control 0 MPU_RGDAAC0 32 bit Base 0x0800 MPU RGD Alternate Access Control 1 MPU_RGDAAC1 32 bit Base 0x0804 MPU RGD Alternate Access Control 2 MPU_RGDAAC2 32 bit...

Страница 1300: ...ter STM_CNT 32 bit Base 0x0004 Reserved Base 0x0008 0x000F STM Channel 0 Control Register STM_CCR0 32 bit Base 0x0010 STM Channel 0 Interrupt Register STM_CIR0 32 bit Base 0x0014 STM Channel 0 Compare...

Страница 1301: ...Base 0x00010 0x001 Miscellaneous Wakeup Control Register ECSM_MWCR 8 bit Base 0x0013 Reserved Base 0x0014 0x001E Miscellaneous Interrupt Register ECSM_MIR 8 bit Base 0x001F Reserved Base 0x0020 0x0023...

Страница 1302: ...ase 0x006C Reserved Base 0x0070 0x3FFF INTC Section 21 5 Memory map and register description 0xFFF4_8000 Block Configuration Register INTC_PBCR 32 bit Base 0x0000 Reserved Base 0x0004 0x0007 Current P...

Страница 1303: ...C_PSR68_71 32 bit Base 0x0084 Priority Select Register INTC_PSR72_75 32 bit Base 0x0088 Priority Select Register INTC_PSR76_79 32 bit Base 0x008C Priority Select Register INTC_PSR80_83 32 bit Base 0x0...

Страница 1304: ...er INTC_PSR196_199 32 bit Base 0x0104 Priority Select Register INTC_PSR200_203 32 bit Base 0x0108 Priority Select Register INTC_PSR204_207 32 bit Base 0x010C Priority Select Register INTC_PSR208_211 3...

Страница 1305: ...er INTC_PSR324_327 32 bit Base 0x0184 Priority Select Register INTC_PSR328_331 32 bit Base 0x0188 Priority Select Register INTC_PSR332_335 32 bit Base 0x018C Priority Select Register INTC_PSR336_339 3...

Страница 1306: ...0x0200 Priority Select Register INTC_PSR452_455 32 bit Base 0x0204 Priority Select Register INTC_PSR456_459 32 bit Base 0x0208 Priority Select Register INTC_PSR460_463 32 bit Base 0x020C Priority Sele...

Страница 1307: ...ister RSER 32 bit Base 0x0030 PUSH TX FIFO Register PUSHR 32 bit Base 0x0034 POP RX FIFO Register POPR 32 bit Base 0x0038 DSPI Transmit FIFO Registers TXFR0 32 bit Base 0x003C DSPI Transmit FIFO Regis...

Страница 1308: ...TXFR0 32 bit Base 0x003C DSPI Transmit FIFO Registers TXFR1 32 bit Base 0x0040 DSPI Transmit FIFO Registers TXFR2 32 bit Base 0x0044 DSPI Transmit FIFO Registers TXFR3 32 bit Base 0x0048 Reserved Bas...

Страница 1309: ...per MB Base 0x0080 Message Buffer 1 MB1 128 bits per MB Base 0x0090 Message Buffer 2 MB2 128 bits per MB Base 0x00A0 Message Buffer 3 MB3 128 bits per MB Base 0x00B0 Message Buffer 4 MB4 128 bits per...

Страница 1310: ...age Buffer 16 MB16 128 bits per MB Base 0x0180 Message Buffer 17 MB17 128 bits per MB Base 0x0190 Message Buffer 18 MB18 128 bits per MB Base 0x01A0 Message Buffer 19 MB19 128 bits per MB Base 0x01B0...

Страница 1311: ...Base 0x0260 Message Buffer 31 MB31 128 bits per MB Base 0x0270 Message Buffer 32 MB32 128 bits per MB Base 0x0280 Message Buffer 33 MB33 128 bits per MB Base 0x0290 Message Buffer 34 MB34 128 bits per...

Страница 1312: ...0x0020 Interrupt Mask High Register IMRH 32 bit Base 0x0024 Interrupt Mask Low Register IMRL 32 bit Base 0x0028 Interrupt Flag High Register IFRH 32 bit Base 0x002C Interrupt Flag Low Register IFRL 32...

Страница 1313: ...Buffer 12 MB12 128 bits per MB Base 0x0140 Message Buffer 13 MB13 128 bits per MB Base 0x0150 Message Buffer 14 MB14 128 bits per MB Base 0x0160 Message Buffer 15 MB15 128 bits per MB Base 0x0170 Mes...

Страница 1314: ...age Buffer 26 MB26 128 bits per MB Base 0x0220 Message Buffer 27 MB27 128 bits per MB Base 0x0230 Message Buffer 28 MB28 128 bits per MB Base 0x0240 Message Buffer 29 MB29 128 bits per MB Base 0x0250...

Страница 1315: ...age Buffer 40 MB40 128 bits per MB Base 0x0300 Message Buffer 41 MB41 128 bits per MB Base 0x0310 Message Buffer 42 MB42 128 bits per MB Base 0x0320 Message Buffer 43 MB43 128 bits per MB Base 0x0330...

Страница 1316: ...age Buffer 54 MB54 128 bits per MB Base 0x03E0 Message Buffer 55 MB55 128 bits per MB Base 0x03F0 Message Buffer 56 MB56 128 bits per MB Base 0x0400 Message Buffer 57 MB57 128 bits per MB Base 0x0410...

Страница 1317: ...ase 0x08AC RX Individual Mask Register 12 RXIMR12 32 bit Base 0x08B0 RX Individual Mask Register 13 RXIMR13 32 bit Base 0x08B4 RX Individual Mask Register 14 RXIMR14 32 bit Base 0x08B8 RX Individual M...

Страница 1318: ...Register 42 RXIMR42 32 bit Base 0x0928 RX Individual Mask Register 43 RXIMR43 32 bit Base 0x092C RX Individual Mask Register 44 RXIMR44 32 bit Base 0x0930 RX Individual Mask Register 45 RXIMR45 32 bi...

Страница 1319: ...bits per MB Base 0x0300 Message Buffer 41 MB41 128 bits per MB Base 0x0310 Message Buffer 42 MB42 128 bits per MB Base 0x0320 Message Buffer 43 MB43 128 bits per MB Base 0x0330 Message Buffer 44 MB44...

Страница 1320: ...0 Message Buffer 57 MB57 128 bits per MB Base 0x0410 Message Buffer 58 MB58 128 bits per MB Base 0x0420 Message Buffer 59 MB59 128 bits per MB Base 0x0430 Message Buffer 60 MB60 128 bits per MB Base 0...

Страница 1321: ...r 16 RXIMR16 32 bit Base 0x08C0 RX Individual Mask Register 17 RXIMR17 32 bit Base 0x08C4 RX Individual Mask Register 18 RXIMR18 32 bit Base 0x08C8 RX Individual Mask Register 19 RXIMR19 32 bit Base 0...

Страница 1322: ...XIMR47 32 bit Base 0x093C RX Individual Mask Register 48 RXIMR48 32 bit Base 0x0940 RX Individual Mask Register 49 RXIMR49 32 bit Base 0x0944 RX Individual Mask Register 50 RXIMR50 32 bit Base 0x0948...

Страница 1323: ...Register Map MPC5606S Microcontroller Reference Manual Rev 7 Freescale Semiconductor 1321...

Страница 1324: ...Register Map MPC5606S Microcontroller Reference Manual Rev 7 1322 Freescale Semiconductor...

Страница 1325: ...Configurable Enhanced Modular IO Subsystem eMIOS200 Removed REDC block from Figure 9 4 eMIOS200 block diagram Removed bullet item One Real Time Signal Bus Client REDC from Section 9 2 2 Features Remo...

Страница 1326: ...Module Disable mode removed bullet The Module Disable mode can also be initiated by hardware A power management block can initiate Module Disable mode by asserting the ipg_doze signal while the DOZE b...

Страница 1327: ...ed this text from first paragraph of Modes of operation section and STOP when it may be disabled by the SWT_CR STP bit If the STP bit is set the counter is stopped in STOP mode otherwise it continues...

Страница 1328: ...uring BAM execution the CPU may be stalled and it will be necessary to generate an external reset to recover ERR003022 In the Download 64 bit password and password check section second bulleted list S...

Страница 1329: ...ced the first bulleted list ERR000575 ERR001103 DMA Channel Mux DMACHMUX In DMACHMUX request assignments table set request 53 to reserved Error Correction Status Module ECSM Corrected AIPS to PBRIDGE...

Страница 1330: ...nces of destructive reset assertion to power on reset In Destructive Event Status Register RGM_DES section added NOTE Clearing each flag in this register requires two clock cycles because of a synchro...

Страница 1331: ...tion settings table changed the INPSAMP value associated with AD_clk fmax 32 4 was 6h is 7h Clock Description Replaced QSPI with QuadSPI In the Clock architecture section changed 32 kHz to 32 KHz Revi...

Страница 1332: ...APIVAL field description In the RTCC CLKSEL field description changed 32 kHz to 32 KHz In the API functional description section changed When the counter reaches the offset count to When the counter r...

Страница 1333: ...section changed The only parts of the device that are still powered to By default the only parts of the device that are still powered Changed the ME_HALT_MC MVRON field from read only to read write Ch...

Страница 1334: ...e Functional description Programming considerations section revised the Modify Operation section This includes a complete replacement of the Margin Read subsection and deletion of the Read Reset subse...

Страница 1335: ...ions to match its contents Revised the MIDR2 PARTNUM field description Error Correction Status Module Replaced references to sleep mode with references to low power mode System Timer Module Added a ST...

Страница 1336: ...on this device Deleted the Operation in Halt Mode section Renamed Operation in Stop Mode to Operation in SMC Stop Mode Corrected several entries in the Impact of MCCTL1 RECIRC and MCDCx SIGN 4 Bit on...

Страница 1337: ...es of operation section and revised the debug information therein Revised the RTCC FRZEN field description Voltage Regulators and Power Supplies Revised the Power supply configuration figure In the Po...

Страница 1338: ...ration figure In the Peripheral clock generation registers table deleted CGM_AC0_DC0 from the DCU entry Corrections throughout the Clock Generation Module MC_CGM section Changed the CR en_pll_sw field...

Страница 1339: ...ry table changed the OPWM entry for the 256 KB device was 12 is 16 Expanded the description of the EMIOSGFLAG EMIOSOUDIS and EMIOSUCDIS registers to show the definitions for each of the two EMIOS modu...

Страница 1340: ...EVTI Generated Break Request section Appendix B Corrected the ADC registers Table C 6 Changes between revisions 1 and 2 Chapter Description Throughout Editorial changes improvements in format and styl...

Страница 1341: ...ised the Low Power RC Oscillator 128 kHz section to reflect the fact that this oscillator remains on in all modes Deleted the LPRC_CTL LPRCON_STDBY bit Deleted the second paragraph of the FMPLL0 1 Ove...

Страница 1342: ...sing field DSPIx_CTARn field descriptions and associated tables Added information to the Delay after Transfer and Continuous Serial Communications Clock sections Removed information relating to DSI an...

Страница 1343: ...Pulse Width and Frequency Modulation Center Aligned Output Pulse Width Modulation with Dead Time Insertion normal and buffered Output Pulse Width Modulation Output Pulse Width Modulation with Trigger...

Страница 1344: ...rated to A rollover interrupt can be generated In the Functional description section deleted the sentence An RTC counter rollover with this bit will cause a wakeup from low power mode Voltage Regulato...

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