NXP Semiconductors MPC5602S, Справочное руководство

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Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 651
PFLASH2P_LCA control state machine completes any flash array access in progress (without signaling
the AHB) before handling a new access request.
17.4.4.6 Access pipelining
The PFLASH2P_LCA controller does not support access pipelining since this capability is not supported
by the low-cost flash array. As a result, the APC (Address Pipelining Control) field is typically set to the
same value as the RWSC (Read Wait State Control) field for best performance, that is,
Bn_APC = Bn_RWSC. It cannot be less than the RWSC.
17.4.4.7 Flash error response operation
The flash array may signal an error response by asserting bkn_fl_xfr_err to terminate a requested access
with an error. This may occur due to an uncorrectable ECC error, or because of improper sequencing
during program/erase operations. When an error response is received, the PFLASH2P_LCA does
not
update or validate a bank 0 or 2 page read buffer nor the bank1 temporary holding register. An error
response may be signaled on read or write operations. For more information on the specifics related to
signaling of errors, including flash ECC, refer to the low-cost flash array documentation. For additional
information on the system registers which capture the faulting address, attributes, data and ECC
information, see the ECSM chapter.
17.4.4.8 Bank 0 and 2 page read buffers and prefetch operation
The logic associated with banks 0 and 2 of the PFLASH2P_LCA contains four page read buffers which
are used to hold data read from the flash array. Each buffer stores 4 pages (4 x 128b storage) operates
independently, and is filled using a single array access. The buffers are used for both prefetch and normal
demand fetches.
The organization of each page buffer is described below in a pseudo-code representation. The hardware
structure includes the buffer address and valid bit, along with 128 bits of page read data and several error
flags.
struct { // bx_py_page_buffer
reg addr[23:4]; // page address
reg valid; // valid bit
reg rdata[127:0]; // page read data
reg xfr_error; // transfer error indicator from flash array
reg multi_ecc_error; // multi-bit ECC error indicator from flash array
reg single_ecc_error; // single-bit correctable ECC indicator from flash array
} bx_py_page_buffer[4];
Given this definition, the PFLASH2P_LCA includes four instantiations of the basic 4 x 128b page buffer.
These are named: b0_p0, b0_p1, b2_p0 and b2_p1.
For the general case, a page buffer is written at the completion of an error-free flash access and the valid
bit asserted. Subsequent flash accesses that “hit” the buffer, that is, the current access address matches the
address stored in the buffer, can be serviced in 0 AHB wait-states as the stored read data is routed from the
given page buffer back to the requesting bus master.