NXP Semiconductors MPC5602S, Справочное руководство

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Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 331
Refer to Section 11.8.3.4, transmit First In First Out (TX FIFO) buffering mechanism , and
Section 11.8.3.5, Receive First In First Out (RX FIFO) buffering mechanism , for details on the FIFO
operation. The TX FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO.
Figure 11-23 illustrates the concept of first-in and last-in FIFO entries along with the FIFO counter.
Figure 11-23. TX FIFO pointers and counter
11.9.4.1 Address calculation for the first-in entry and last-in entry in the TX FIFO
The memory address of the first-in entry in the TX FIFO is computed by the following equation:
First-in entry address = TX FIFO base + 4 (TXNXTPTR)
The memory address of the last-in entry in the TX FIFO is computed by the following equation:
Last-in entry address = TX FIFO base + 4
x
[(TXCTR + TXNXTPTR – 1) modulo TX FIFO depth]
where:
TX FIFO base = base address of transmit FIFO
TXCTR = transmit FIFO counter
TXNXTPTR = transmit next pointer
TX FIFO depth = transmit FIFO depth, implementation specific
11.9.4.2 Address calculation for the first-in entry and last-in entry in the RX FIFO
The memory address of the first-in entry in the RX FIFO is computed by the following equation:
First-in entry address = RXFIFO base + 4
x
(POPNXTPTR)
The memory address of the last-in entry in the RX FIFO is computed by the following equation:
Last-in entry address = RXFIFO base + 4
x
[(RXCTR + POPNXTPTR – 1) modulo RXFIFO depth]
where:
RXFIFO base = base address of receive FIFO
RXCTR = receive FIFO counter
POPNXTPTR = pop next pointer
Entry C
Entry A (first in)
– 1
Entry B
Entry D (last in)
TX FIFO base
Push TX FIFO
TX FIFO counter
Shift register SOUT
register
Transmit next
data pointer
–
–
–
–
+ 1
(TXNXTPTR)