NXP Semiconductors MPC5602S, Справочное руководство

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Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
472 Freescale Semiconductor
typedef union {
struct { /* biter.e_link = 1 */
unsigned short biter.linkch:6; /* link channel number, */
unsigned short biter:9; /* beginning (“major”) iteration count */
} init_minor_link_enabled; /* channel link at end of the minor loop */
struct { /* biter.e_link = 0 */
unsigned short biter:15; /* beginning (“major”) iteration count */
} init_minor_link_disabled; /* no linking at end of the minor loop */
} t_minor_link_biter;
typedef struct {
unsigned intsaddr;/* source address */
unsigned intsmod:5;/* source address modulo */
unsigned intssize:3;/* source transfer size */
unsigned intdmod:5;/* destination address modulo */
unsigned intdsize:3;/* destination transfer size */
short soff; /* signed source address offset */
unsigned intnbytes;/* inner (“minor”) byte count */
int slast; /* last source address adjustment */
unsigned intdaddr;/* destination address */
unsigned shortciter.e_link:1;/* enable channel linking on minor loop */
t_minor_link_citerminor_link_citer;/* conditional current iteration count */
short doff; /* signed destination address offset */
int dlast_sga;/* last destination address adjustment, or
scatter/gather address (if e_sg = 1) */
unsigned shortbiter.e_link:1;/* beginning channel link enable */
t_minor_link_biterminor_link_biter;/* beginning (“major”) iteration count */
unsigned intbwc:2;/* bandwidth control */
unsigned intmajor.linkch:6;/* link channel number */
unsigned intdone:1;/* channel done */
unsigned intactive:1;/* channel executing */
unsigned intmajor.e_link:1;/* enable channel linking on major loop*/
unsigned inte_sg:1;/* enable scatter/gather descriptor */
unsigned intd_req:1;/* disable ipd_req when done */
unsigned intint_half:1;/* interrupt on citer = (biter >> 1) */
unsigned intint_maj:1;/* interrupt on major loop completion */
unsigned intstart:1;/* explicit channel start */
} tcd /* transfer_control_descriptor */
The basic operation of a channel is defined as:
1. The channel is initialized by software loading the transfer control descriptor into the DMA’s
programming model, memory-mapped through the IPS space, and implemented as local memory.
2. The channel requests service; either explicitly by software, a peripheral request or a linkage from
another channel.
NOTE
The major loop executes one iteration per service request.
3. The contents of the transfer control descriptor for the activated channel is read from the local memory
and loaded into the DMA engine’s internal register file.
4. The DMA engine executes the data transfer defined by the transfer control descriptor, reading from the
source and writing to the destination. The number of iterations in the minor loop is automatically
calculated by the DMA engine. The number of iterations within the minor loop is a function of the number