NXP Semiconductors MPC5602S, Справочное руководство

Страница: 638 / 1344

Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
636 Freescale Semiconductor
17.4.1.1 Overview
The PFLASH2P_LCA supports a 32-bit data bus width at the two AHB ports and connections to 128-bit
read data interfaces from three memory
banks , where each bank contains one (or more) instantiations of
the low-cost flash memory array. Typically, flash bank0 is connected to the first code flash memory, bank2
is connected to a second code flash memory, and bank1 is connected to the optional data flash memory.
The memory controller capabilities vary between the banks with each bank’s functionality optimized for
the typical use cases associated with the attached flash memory. As an example, the PFLASH2P_LCA
logic associated with bank0 contains 2 four-entry “page” buffers, one for each AHB input port, where each
buffer entry contains 128 bits of data (1 flash page) plus an associated controller which prefetches
sequential lines of data from the flash array into the buffer. This structure is repeated for bank2, providing
a total of four copies of the 4-entry page buffer. The controller logic associated with bank1 is simpler and
only supports two 128-bit registers (again, one for each AHB port) which serve as temporary page holding
registers and no support of any prefetching. Prefetch buffer hits from any of the page buffers or temporary
holding registers support zero-wait AHB data phase responses. AHB read requests which miss the buffers
generate the needed flash array access and the read data is forwarded to the AHB port upon completion,
typically incurring two wait-states at an operating frequency of 60
–
64 MHz. The logic of the
PFLASH2P_LCA is structured to support simultaneous AHB accesses from the two ports fully in parallel
when the references are targeted to different memory banks.
If simultaneous AHB accesses reference the
same bank, then arbitration logic within the PFLASH2P_LCA determines the order the references are
granted access to the bank.
This memory controller is optimized for applications where a cacheless processor core, such as the
e200z0h, is connected through the platform to on-chip memories, e.g., flash and RAM, where the
processor and platform operate at the same frequency. For these applications, the 2-stage pipeline
AMBA-AHB system bus is effectively mapped directly into stages of the processor’s pipeline and zero
wait-state responses for most memory accesses are critical for providing the required level of system
performance.
17.4.1.2 Features
The following list summarizes the key features of the PFLASH2P_LCA:
• Triple bank interfaces support up to a total of 16 Mbytes of flash memory, partitioned as two 4
Mbyte code banks (0, 2) and a separate optional 8 Mbyte data bank (1)
• Dual AHB input port interfaces support a 32-bit data bus. All AHB aligned and unaligned reads
within the 32-bit container are supported. Only aligned word writes are supported.
• Array interfaces support a 128-bit read data bus and a 64-bit write data bus for each of the 3 banks
• Internal hardware structure supports fully concurrent accesses from the dual AHB input ports when
accessing different flash banks
— If the AHB ports reference the same flash bank, there is arbitration logic which determines the
order the accesses are granted access to the bank
— Programmable arbitration allows the user to select fixed priority or round-robin
• Total flash page storage in the PFLASH2P_LCA includes four 4-entry page buffers (b0_p0, b0_p1,
b2_p0, b2_p1) and two 128-bit temporary holding registers (b1_p0, b1_p1).