NXP Semiconductors MPC5602S, Справочное руководство

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Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
654 Freescale Semiconductor
17.4.4.9 Bank1 temporary holding registers
Recall the bank1 logic within the PFLASH2P_LCA includes two 128-bit data registers (one for each AHB
port), used for capturing read data. Since this bank does not support prefetching, the read data for the
referenced address is bypassed directly back to the AHB data bus. The page is also loaded into the
appropriate temporary data register and subsequent accesses to this page can hit from this register, if it is
enabled (B1_Py_BFE).
The organization of the temporary holding register is described below in a pseudo-code representation.
The hardware structure includes the buffer address and valid bit, along with 128 bits of page read data and
several error flags and is the same as an individual bank 0 or 2 page buffer.
struct { // b1_py_page_buffer
reg addr[23:4]; // page address
reg valid; // valid bit
reg rdata[127:0]; // page read data
reg xfr_error; // transfer error indicator from flash array
reg multi_ecc_error; // multi-bit ECC error indicator from flash array
reg single_ecc_error; // single-bit correctable ECC indicator from flash array
} b1_py_page_buffer;
Given this definition, the PFLASH2P_LCA includes two instantiations of this temporary holding register
for bank 1. These are named: b1_p0 and b1_p1.
For the general case, a temporary holding register is written at the completion of an error-free flash access
and the valid bit asserted. Subsequent flash accesses that “hit” the buffer, that is, the current access address
matches the address stored in the temporary holding register, can be serviced in 0 AHB wait-states as the
stored read data is routed from the temporary register back to the requesting bus master.
The contents of the holding register are invalidated by the falling edge transition of b1_fl_done and on any
non-sequential access with a non-zero value on haddr[28:24] (to support wait-state emulation) in the same
manner as the bank0 page buffers. Additionally, the B1_Py_BFE register bit can be cleared by software to
invalidate the contents of the holding register.
As noted in Section 17.4.4.7, Flash error response operation , the temporary holding register is not marked
as valid if the flash array access terminated with any type of transfer error. However, the result is that flash
array accesses that are tagged with a single-bit correctable ECC event are loaded into the temporary
holding register and validated. Accordingly, one special case needing software invalidation relates to
holding register “hits” on flash data which was tagged with a single-bit ECC event. Depending on the
specific hardware configuration, the reporting of a single-bit ECC event may generate an ECC alert
interrupt.
In order to prevent repeated ECC alert interrupts, the temporary holding registers need to be
invalidated by software after the first notification of the single-bit ECC event .
Each bank1 temporary holding register effectively operates like a single page buffer.
17.4.4.10 Input port arbitration
For maximum system performance, the PFLASH2P_LCA fully supports concurrent flash accesses from
the two AHB input ports when the references are targeted to different flash banks. This is expected to be