NI PXI-6653, Руководство пользователя

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Chapter 3 Hardware Overview
© National Instruments Corporation 3-13 NI PXI-6653 User Manual
The front panel synchronization clock may be any of the following signals
• DDS clock
• PXI_CLK10
• PFI 0 Input
• Any of the above signals divided by the first frequency divider
(2
n
, up to 512)
• Any of the above signals divided by the second frequency divider
(2
m
, up to 512)
Refer to the Choosing the Type of Routing section for more information on
the synchronization clock.
Note The front panel synchronization clock is the same for all routing operations in which
PFI <0..5> is defined as the output, although the divide-down ratio for this clock (full rate,
first divider, second divider) may be chosen on a per route basis.
Using the PXI/RTSI Triggers
The PXI/RTSI triggers go to all the slots in the chassis. All modules receive
the same PXI/RTSI triggers, so PXI/RTSI trigger 0 is the same for Slot 2
as it is for Slot 3, and so on. This feature makes the PXI/RTSI triggers
convenient in situations where you want, for instance, to start an
acquisition on several devices at the same time because all modules will
receive the same trigger.
The frequency on the PXI/RTSI triggers should not exceed 20 MHz to
preserve signal integrity. The signals do not reach each slot at precisely the
same time. A difference of several nanoseconds between slots can occur in
an eight-slot chassis. However, this delay is not a problem for many
applications. You can route signals to the PXI/RTSI triggers from
PFI <0..5>, from the PXI star triggers, or from other PXI/RTSI triggers.
You also can route PXI_CLK10 or the DDS clock to a PXI/RTSI trigger
line (PXI_TRIG<0..7>) using the synchronization clock.
You can independently select the output signal source for each PXI/RTSI
trigger line from one of the following sources:
• PFI <0..5>
• Another PXI/RTSI trigger <0..7> (PXI_TRIG<0..7>)
• PXI_STAR <0..12>
• Global software trigger
• Backplane synchronization clock