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CHAPTER 8 CLOCK GENERATOR FUNCTIONS
User’s Manual U12688EJ4V0UM00
238
8.5.3 HALT mode
(1) Setting and operating state
In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the CPU’s
operation clock stops. Supply of the clock to other internal peripheral I/O functions is continued and their
operation continues. By setting the HALT mode during the time when CPU is idle, the system’s total power
consumption can be reduced.
Switching to the HALT mode is accomplished by executing the HALT instruction.
In the HALT mode, program execution stops, but all the contents of all the registers, internal RAM, and ports
are held in the state they were in just before the HALT mode was entered. Also, internal peripheral I/O (other
than the ports) that is not dependent on CPU instruction processing continues operation. The state of each
hardware unit when in the HALT mode is shown in Table 8-2.
Remark
Even after HALT instruction execution, instruction fetch operations continue until the internal
instruction prefetch queue becomes full. When the prefetch queue becomes full, it stops in the
state shown in Table 8-2.
Table 8-2. Operating States When in HALT Mode
Function
Operating State
Clock generator
Operating
Internal system clock
Operating
CPU
Stop
Port
Hold
Internal peripheral I/O (except ports)
Operating
Internal data
All the CPU’s registers, status, data, internal RAM
contents and other internal data, etc. are retained in the
state they were in before entering the HALT mode.
D0 to D15
A0 to A23
RD, WE, OE, BCYST
LWR, UWR, IORD, IOWR
CS0 to CS7
RAS0 to RAS7
LCAS, UCAS
REFRQ
HLDRQ
HLDAK
When in
external
expansion
mode
WAIT
Operating
CLKOUT
Clock output (when not in clock output inhibit)
Содержание V850E/MS1 UPD703100
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