NEC V850E/MS1 UPD703100, Руководство пользователя

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CHAPTER 4 BUS CONTROL FUNCTION
User’s Manual U12688EJ4V0UM00
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4.9 Bus Priority Order
There are five external bus cycles: bus hold, instruction fetch, operand data access, DMA cycle and refresh cycle.
Bus hold has the highest priority, then the refresh cycle, DMA cycle, instruction fetch and operand data access, in
descending order.
Between read access and write access in read modify write access, an instruction fetch may be inserted.
Also, between bus access and bus access during CPU bus lock, an instruction fetch may be inserted.
Table 4-2. Bus Priority Order
Priority Order External Bus Cycle Bus Master
Bus hold External device
Refresh cycle DRAM controller
DMA cycle DMA controller
Instruction fetch CPU
High
Low
Operand data access CPU
4.10 Boundary Operation Conditions
4.10.1 Program space
(1) Branching to the peripheral I/O area or successive fetch from the internal RAM area to the internal peripheral
I/O area is prohibited. In terms of hardware, fetching the NOP op code continues, and fetching from the
external memory is not performed.
(2) If a branch instruction exists at the upper limit of the internal RAM area, a pre-fetch operation (invalid fetch)
that straddles over the internal peripheral I/O area does not occur when instruction fetch is performed.
(3) In burst fetch mode, if an instruction fetch is performed for contiguous memory blocks, the burst fetch is
terminated at the upper limit of a block, and the start-up cycle is started at the lower limit of the next block.
(4) Burst fetch is valid only in the external memory area. In memory block 7, it is terminated when the internal
address count value has reached the upper limit of the external memory area.