CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
User’s Manual U12688EJ4V0UM00
145
Figure 5-8. High-Speed Page DRAM Access Timing (3/4)
(c) Write timing 1
T1
T2
Column address
Row
address
Column address
Column address
WAIT
D0 to D15
IOWR
IORD
LWR/LCAS
UWR/UCAS
WE
OE
RD
CSn/RASn
BCYST
A0 to A23
CLKOUT
Data
Data
TO1
TO2
TO1
TO2
T3
Data
Remarks 1. This is the timing in the case of no waits.
2. The circle indicates the sampling timing.
3. The broken lines indicate high impedance.
4. n = 0 to 7
Содержание V850E/MS1 UPD703100
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