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CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
User’s Manual U12688EJ4V0UM00
266
Figure 9-4. Relationship Between Clear/Start by TCLR1n Signal Input and Overflow Operation
(If ECLR1n = 1 and OSTn = 1)
TM1n
0
Count
start
INTOV1n
TCLR1n
CE1n 1
Overflow
FFFFH
TCLR1n
TCLR1n
Remark
n = 0 to 5
9.4.5 Capture operation
In synch with an external trigger, a capture operation is performed in which the TM1n count value is captured and
held in the capture register asynchronous to the count clock (n = 0 to 5). The active edge detected from external
interrupt request input pins INTP1n0 to INTP1n3 is used as the external trigger (capture trigger). In synch with that
capture trigger signal, the count value of TM1n, as it is counting, is captured and held in the capture register. The
value in the capture register is held until the next capture trigger is generated.
Also, interrupt requests (INTCC1n0 to INTCC1n3) are generated from the INTP1n0 to INTP1n3 signal inputs.
Table 9-2. Capture Trigger Signals (TM1n) to 16-Bit Capture Registers
Capture Register
Capture Trigger Signal
CC1n0
INTP1n0
CC1n1
INTP1n1
CC1n2
INTP1n2
CC1n3
INTP1n3
Remarks 1. CC1n0 to CC1n3 are the capture/compare registers. Which register is used is specified in timer
unit mode register 1n (TUM1n).
2. n = 0 to 5
Содержание V850E/MS1 UPD703100
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