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CHAPTER 8 CLOCK GENERATOR FUNCTIONS
User’s Manual U12688EJ4V0UM00
246
8.6.2 Time base counter (TBC)
The time base counter (TBC) is used to secure the oscillation stabilization time of the oscillator when the software
STOP mode is released.
••••
Resonator connection time (PLL Mode, and CESEL bit of the PSC Register = 0)
After releasing the software STOP mode, the oscillation stabilization time is counted by the TBC and after
counting is ended, program execution begins.
The TBC count clock is selected by the TBCS bit in the PSC register, and it is possible to set the following count
times (refer to 8.5.2 (1) Power save control register (PSC)).
Table 8-6. Example of Count Time (
φφφφ
= 5
××××
f
XX
)
Count Time
f
XX
= 3.2768 MHz
f
XX
= 5.0000 MHz
f
XX
= 6.5536 MHz
f
XX
= 8.0000 MHz
TBCS Bit
Count Clock
φ
= 16.384 MHz
φ
= 25.000 MHz
φ
= 32.768 MHz
φ
= 40.000 MHz
0
f
XX
/2
8
20.0 ms
13.1 ms
10.0 ms
8.1 ms
1
f
XX
/2
9
40.0 ms
26.2 ms
20.0 ms
16.3 ms
f
XX
: External resonator frequency
φ
:
Internal system clock frequency
Содержание V850E/MS1 UPD703100
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