CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
User’s Manual U12688EJ4V0UM00
190
6.8
DMA Channel Priorities
The DMA channel priorities are fixed, as follows:
DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3
These priorities are valid in the TI state only. In block transfer mode, the channel used for transfer is never
switched.
In single-step transfer mode, if a higher priority DMA transfer request is issued while the bus is released (in the TI
state), the higher priority DMA transfer request is accepted.
6.9
Next Address Setting Function
The DMA source address registers (DSAnH, DSAnL) DMA destination address registers (DDAnH, DDAnL) and
DMA byte count register (DBCn) are buffer registers with a 2-stage FIFO configuration (n = 0 to 3).
When the terminal count is issued, these registers are rewritten with the value that was set just previously.
Therefore, during DMA transfer, these registers’ contents do not become valid even if they are rewritten. When
starting DMA transfer with the rewritten contents of these registers, set the ENn bit (1) of the DCHCn register.
Figure 6-10 shows the buffer register configuration.
Figure 6-10. Buffer Register Configuration
Reading of data
Writing of data
Master
register
Slave
register
Address/
count
controller
Internal bus
Содержание V850E/MS1 UPD703100
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