NEC mPD178053, Руководство пользователя

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CHAPTER 13 PLL FREQUENCY SYNTHESIZER
User’s Manual U15104EJ2V0UD
13.5 PLL Disable Status
The PLL frequency synthesizer can be stopped (PLL disabled status) by performing any of the following settings
while the PLL frequency synthesizer is operating.
• Setting value of bit 3 (PLLRF3) of the PLL reference mode register (PLLRF) to 1 to set PLL disabled status
• Setting STOP mode with the STOP instruction
• Setting reset status with the reset function
The following table shows the operation of each block and the status of each register in the PLL disabled status.
Table 13-4. Operation of Each Block and Register Status in PLL Disabled Status
Block/Register Status in PLL Disabled Status
VCOL and VCOH pins Status set in bit 3 (VCOHDMD) and bit 2
(VCOLDMD) of PLLMD
Programmable divider Division stops
Reference frequency generator Output stops
Phase comparator Output stops
EO0 and EO1 pin High impedance
PLL mode select register Retains value on execution of write instruction
PLL data register
PLL unlock F/F judge register
13.6 Notes on PLL Frequency Synthesizer
• Notes on using PLL frequency synthesizer
Because the input pins (VCOL and VCOH pins) of the PLL frequency synthesizer are provided with an AC
amplifier, cut the DC component of the input signal by connecting a capacitor to the input pins in series.
The potential of the selected input pin is intermediate (about 1/2V
DD
). The input pin not selected becomes the
status set in bit 3 (VCOHDMD) and bit 2 (VCOLDMD) of the PLL mode select register (PLLMD).
For the frequencies that can be actually input and input amplitude, refer to CHAPTER 19 ELECTRICAL
SPECIFICATIONS.