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CHAPTER 10 A/D CONVERTER
User’s Manual U15104EJ2V0UD
Figure 10-9. A/D Conversion Operation in Power-Fail Comparison Mode (3/3)
(3) In HALT repeat mode (when generation of interrupt (INTAD3) is not used to release HALT mode)
Notes 1. The conversion data is undefined immediately after bit 7 (ADCS3) of A/D converter mode register
3 (ADM3) is set to 1 (to start conversion).
2. When executing A/D conversion in the HALT mode by using the power-fail HALT repeat mode,
clear the interrupt request flag (ADIF) after the first conversion has been completed immediately
after bit 7 (ADCS3) of ADM3 has been set to 1, and bit 5 (PFHRM3) of power-fail comparison mode
register 3 (PFM3) has been set to 1, before executing the HALT instruction.
3. The first result of the A/D conversion (A/D conversion result and interrupt request) is not correct.
Do not use this result because there is a possibility that it will be determined that the comparison
condition has matched even if it has not.
Caution
Be sure to set bit 5 (PFHRM3) of PFM3 to 1 (to enable the HALT repeat mode setting).
Remark
n = 0, 1, ... 5
A/D conversion
ADCR3
Stop
Comparison condition
matches
(PFHRM3 is reset)
ANIn
ANIn
ANIn
ANIn
ANIn
Unde-
fined
Note 1
ANIn
Previous
conversion
result
A/D conversion is in progress but
conversion operation is stopped
Previous
conversion
result
...
Conversion starts
ADCS3 = 1
ADIF clear
PFHRM3 = 1
HALT instruction
Note 2
HALT operation
Interrupt request (INTAD) does
not release HALT mode
INTAD3
(when PFEN3 = 1)
Comparison
condition does
not match
Note 3
...
PFT3, PFM3
set
Содержание mPD178053
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