26
CHAPTER 1 OUTLINE
User’s Manual U15104EJ2V0UD
1.6 Block Diagram
Remarks 1. The internal ROM capacity differs depending on the product.
2. ( ):
µ
PD178F054
8-bit timer/
event counter50
8-bit timer/
event counter51
Serial
interface30
Interrupt
control
System
control
Serial
interface32
Voltage
regulator
Watchdog timer
Basic timer
Port 0
Port 1
Port 3
Port 4
Port 5
Port 6
Port 7
Port 12
Port 13
7
6
8
8
8
8
8
6
5
3
6
PLL
A/D converter
Frequency
counter
PLL
voltage
regulator
Buzzer output
78K/0
CPU
Core
RAM
1024 bytes
ROM
Flash
memory
TI50/P33
TO50/P130
P00 to P06
P10 to P15
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P77
P120 to P125
P130 to P132
ANI0/P10 to
ANI5/P15
AMIFC
FMIFC
EO0
EO1
VCOL
VCOH
V
DD
PLL
GNDPL
IC (V
pp
)
L
SI30/P70
SO30/P71
SCK30/P72
Serial
interface31
SI31/P74
SO31/P75
SCK31/P76
SI32/P120
SO32/P121
SCK32/P122
SI321/P123
SO321/P124
SCK321/P125
INTP0/P00 to
INTP4/P04
BEEP0/P36
BUZ/P37
RESET
X1
X2
V
DD
PORT
GNDPORT
V
DD
RESET
CPU
PERIPHERAL
V
OSC
V
CPU
REGOSC
REGCPU
GND
TI51/P34
TO51/P131
8-bit timer/
event counter52
8-bit timer53
TI52/P77
TO52/P132
Содержание mPD178053
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