CHAPTER 5 CLOCK GENERATOR
Preliminary User’s Manual U16846EJ1V0UD
86
(3) Main clock mode register (MCM)
This register sets the CPU clock (high-speed system clock/Ring-OSC clock).
MCM can be set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 5-4. Format of Main Clock Mode Register (MCM)
Address: FFA1H After reset: 00H R/W
Note
Symbol
7 6 5 4 3 2
<1>
<0>
MCM
0 0 0 0 0 0
MCS
MCM0
MCS
CPU
clock
status
0
Operates with Ring-OSC clock
1
Operates
with
high-speed system clock
MCM0
Selection of clock supplied to CPU
0
Ring-OSC
clock
1
High-speed system clock
Note Bit 1 is read-only.
Caution When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the
divided clock of the Ring-OSC oscillator output (f
X
) is supplied to the peripheral
hardware (f
X
= 240 kHz (TYP.)).
Operation of the peripheral hardware with the Ring-OSC clock cannot be
guaranteed. Therefore, when the Ring-OSC clock is selected as the clock supplied
to the CPU, do not use peripheral hardware. In addition, stop the peripheral
hardware before switching the clock supplied to the CPU from the high-speed
system clock to the Ring-OSC clock. Note, however, that the following peripheral
hardware can be used when the CPU operates on the Ring-OSC clock.
•
Watchdog timer
•
Clock
monitor
•
8-bit timer H1 when f
R
/2
7
is selected as the count clock
•
Peripheral hardware with an external clock selected as the clock source
(Except when the external count clock of TM00 is selected (TI000 valid edge))
