CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50
Preliminary User’s Manual U16846EJ1V0UD
152
7.4.4 Operation as PWM output
8-bit timer/event counter 50 operates as a PWM output when bit 6 (TMC506) of 8-bit timer mode control register 50
(TMC50) is set to 1.
The duty pulse is determined by the value set to 8-bit timer compare register 50 (CR50).
Set the active level width of the PWM pulse to CR50; the active level can be selected with bit 1 of TMC50
(TMC501).
The count clock can be selected with bits 0 to 2 (TCL500 to TCL502) of timer clock selection register 50 (TCL50).
PWM output can be enabled/disabled with bit 0 of TMC50 (TOE50).
Caution In PWM mode, make the CR50 rewrite period 3 count clocks of the count clock (clock selected by
TCL50) or more.
(1) PWM output basic operation
Setting
<1> Set each register.
•
Set the port output latch (P17) and port mode register 1 (PM17) to 0.
•
TCL50: Select the count clock.
•
CR50: Compare
value
•
TMC50: Stop the count operation, select PWM mode.
The timer output F/F is not changed, timer output is enabled.
TMC501
Active Level Selection
0 Active-high
1 Active-low
(TMC50 = 01000001B or 01000011B)
<2> The count operation starts when TCE50 = 1.
Set TCE50 to 0 to stop the count operation.
PWM output operation
<1> PWM output (output from TO50) outputs an inactive level until an overflow occurs.
<2> When an overflow occurs, the active level is output.
The active level is output until CR50 matches the count value of 8-bit timer counter 50 (TM50).
<3> After the CR50 matches the count value, the inactive level is output until an overflow occurs again.
<4> Operations <2> and <3> are repeated until the count operation stops.
<5> When the count operation is stopped with TCE50 = 0, PWM output becomes inactive.
For details of timing, see Figures 7-10 and 7-11.
The cycle, active-level width, and duty are as follows.
•
Cycle = 2
8
t
•
Active-level width = Nt
•
Duty = N/2
8
(N = 00H to FFH)
