CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50
Preliminary User’s Manual U16846EJ1V0UD
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(2) Operation with CR50 changed
Figure 7-11. Timing of Operation with CR50 Changed
(a) CR50 value is changed from N to M before clock rising edge of FFH
→
Value is transferred to CR50 at overflow immediately after change.
Count clock
TM50
CR50
TCE50
INTTM50
TO50
<1> CR50 change (N
→
M)
N N + 1 N + 2
FFH 00H 01H
M M + 1 M + 2
FFH 00H 01H 02H
M M + 1 M + 2
N
02H
M
H
<2>
t
(b) CR50 value is changed from N to M after clock rising edge of FFH
→
Value is transferred to CR50 at second overflow.
Count clock
TM50
CR50
TCE50
INTTM50
TO50
N N + 1 N + 2
FFH 00H 01H
N N + 1 N + 2
FFH 00H 01H 02H
N
02H
N
H
M
M M+1 M+2
<1> CR50 change (N
→
M)
<2>
t
Caution When reading from CR50 between <1> and <2> in Figure 7-11, the value read differs from the
actual value (read value: M, actual value of CR50: N).
7.5 Cautions for 8-Bit Timer/Event Counter 50
(1) Timer start error
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because 8-bit timer counter 50 (TM50) is started asynchronously to the count clock.
Figure 7-12. 8-Bit Timer Counter 50 Start Timing
Count clock
TM50 count value
00H
01H
02H
03H
04H
Timer start
