CHAPTER 18 POWER-ON-CLEAR CIRCUIT
Preliminary User’s Manual U16846EJ1V0UD
320
18.4 Cautions for Power-on-Clear Circuit
In a system where the supply voltage (V
DD
) fluctuates for a certain period in the vicinity of the POC detection
voltage (V
POC
), the system may be repeatedly reset and released from the reset status. In this case, the time from
release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
Figure 18-3. Example of Software Processing After Release of Reset (1/2)
•
If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
Yes
Power-on-clear
; The
Ring-OSC clock is set as the CPU clock when the reset signal is generated
;
The cause of reset (power-on-clear, WDT, LVI, or clock monitor)
can be identified by the RESF register.
;
Change the CPU clock from the Ring-OSC clock to the high-speed system
clock.
;
Check the stabilization of oscillation of the high-speed system clock by using
the OSTC register
Note 3
.
;
TMIFH1 = 1: Interrupt request is generated.
;
Initialization of ports
;
8-bit timer H1 can operate with the Ring-OSC clock.
Source: f
R
(480 kHz (MAX.))/2
7
×
compare value 200 = 53 ms
(f
R
: Ring-OSC clock oscillation frequency)
No
Note 1
Reset
Checking cause
of reset
Note 2
Check stabilization
of oscillation
Change CPU clock
50 ms has passed?
(TMIFH1 = 1?)
Initialization
processing
Start timer
(set to 50 ms)
Notes 1. If reset is generated again during this period, initialization processing is not started.
2. A flowchart is shown on the next page.
3. Waiting for the oscillation stabilization time is not required when the external RC oscillation clock is
selected as the high-speed system clock by the option byte. Therefore, the CPU clock can be
switched without reading the OSTC value.
