COMPONENT MAINTENANCE MANUAL
AVIATION PRODUCTS
Model FA5000
Rev. 02 Page 139
July 21/17
Testing & Fault Isolation
23–70
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30
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8.
MAIN PROCESSOR
Table 103. Main Processor Troubleshooting Chart
Item
ID
Function Type
Failure
Mode
Local Effect
Next Effect
End Effect
A001
−
DSP
Watch Dog Timer;
ARINC 429 RX/TX; Did-
crete I/Ps and O/Ps;
FDR Data; Frequency
Counter; CSMU Inter-
face; Power Supply
Status
Over/Under
Voltage
The DSP fails:
No program
execution or
storage;
FPGA, all re-
gisters and all
interfaces fail
The MP PWA
fails to operate
The CVDR fails to operate
Watch Dog Timer;
ARINC 429 RX/TX; Did-
crete I/Ps and O/Ps;
FDR Data; Frequency
Counter; CSMU Inter-
face; Power Supply
Status
Incorrect O/P The DSP fails:
No program
execution or
storage;
FPGA, all re-
gisters and all
interfaces fail
The MP PWA
fails to operate
The CVDR fails to operate
Watch Dog Timer;
ARINC 429 RX/TX; Did-
crete I/Ps and O/Ps;
FDR Data; Frequency
Counter; CSMU Inter-
face; Power Supply
Status
Single Event
Upset (SEU)
The DSP ini-
tially does not
operate
The MP PWA
initially does
not operate
The CVDR initially does not op-
erate: some data may be cor-
rupt, lost and/or may not be re-
corded, stored or copied
NOTE: After the Watch Dog
Timer has timed out, it forces
the system to reset
A002
−
FPGA
Watch Dog Timer;
ARINC 429 RX/TX; Did-
crete I/Ps and O/Ps;
FDR Data; Frequency
Counter; CSMU Inter-
face; Power Supply
Status
Over/Under
Voltage
The FPGA
fails: The sys-
tem is unable
to reboot
The MP PWA
fails to operate
The CVDR fails to operate
Watch Dog Timer;
ARINC 429 RX/TX; Did-
crete I/Ps and O/Ps;
FDR Data; Frequency
Counter; CSMU Inter-
face; Power Supply
Status
Incorrect O/P The FPGA
fails: The sys-
tem is unable
to reboot
The MP PWA
fails to operate
The CVDR fails to operate
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