Appendix C: Status model
Models 707B and 708B Switching Matrix Reference Manual
C-2
707B-901-01 Rev. A / August 2010
Status Byte register
The Status Byte register receives summary bits from the other status register sets and queues, and
also from itself (which sets the Master Summary Status, or MSS, bit). The register sets are structured
in the following manner:
- Status Byte Register (byte containing the following bits)
- - Bit 0: Measurement summary register sets the Measurement Summary Bit (MSB)
- - Bit 1: System summary register sets the System Summary Bit (SSB)
- - Bit 2: Error/Event queue sets the Error Available bit (EAV)
- - Bit 3: Questionable summary register sets the Questionable Summary Bit (QSB)
- - Bit 4: Output queue sets the Message Available bit (MAV)
- - Bit 5: Event summary register sets the Event Summary Bit (ESB)
- - Bit 6: Master summary status register sets the Master Summary Status bit (MSS) or a Service
request sets the RQS bit.
- - Bit 7: Operation summary register sets the Operation Summary Bit (OSB) (byte containing the
following bit):
- - - Operation user summary register (sets the User bit of the Operation Summary register)
Status register sets
Typically, a status register set contains the following registers:
•
Condition
(.condition): a read-only register that constantly updates to reflect the present
operating conditions of the instrument.
•
Enable register
(.enable): a read-write register that allows a summary bit to be set when an
enabled event occurs.
•
Event register
(.event): a read-only register that sets a bit to 1 when the applicable event occurs.
If the enable register bit for that event is also set, the summary bit of the register will set to 1.
•
Negative transition register
(.ntr): a read-write register that when set to 1, specifies a negative
transition (change from 1 to 0) sets the event register bit.
•
Positive transition register
(.ptr): a read-write register that when set to 1, specifies a positive
transition (change from 0 to 1) sets the event register bit.
When an event occurs, and the appropriate NTR or PTR bit is set, the matching event register bit is
set to 1. The event bit remains latched to 1 until the register is read or the status model is reset. When
an event register bit is set and its corresponding enable bit is set, the output (summary bit) of the
register will set to 1. This in turn sets a bit in a higher-level register cascading to the associated
summary bit of the Status Byte register.
