Appendix C: Status model
Models 707B and 708B Switching Matrix Reference Manual
C-8
707B-901-01 Rev. A / August 2010
Questionable summary bit (Questionable event register)
Figure 100: Questionable summary bit (Questionable event register)
See the Questionable Summary Bit
in the Status Byte register overview.
0
7
14
13
12
11
10
9
8
15
+
Questionable Summary Bit
*
status.questionable.event
status.questionable.enable
&
status.questionable.S1THR
status.questionable.S2THR
status.questionable.S3THR
status.questionable.S4THR
status.questionable.S5THR
status.questionable.S6THR
Legend
Summary Message Bit: A single bit indicating one or more enabled
events
occured.
Performs a logical AND of input bits, with the result feeding the
Summary Message Bit.
Bit not used (returns a value of 0 when read).
+
&
As shown above, there is only one register set associated with the questionable status. Attributes are
summarized in
(on page 7-182). Keep in mind that bits can also be set by using
numeric parameter values. For details, see
Programming enable and transition registers
(on page C-
For example, any of the following statements will set the thermal aspect enable bit of a card in slot 1:
status.questionable.enable = status.questionable.S1THR
status.questionable.enable = status.questionable.SLOT1_THERMAL
status.questionable.enable = 512
The following command will request the questionable enable register value in numeric form:
print(status.questionable.enable)
The bits used in this register set are described as follows:
•
SxTHR:
Set bit indicates the thermal aspect of the card in slot x is in question, where x = 1 to 6.
Message available bit (Output queue)
The summary bit of the output queue provides enabled summary information to Bit 4 (MAV) of the
status byte.
The Message Available Bit (MAV) is set when the Output queue holds data that pertains to the normal
operation of the instrument. The Output queue is one of the two Switching Matrix queues associated
with the status model. The other queue sets the
Error Available Bit (Error or Event queue)
(on page
C-7). Both queues are first-in, first-out (FIFO) queues. The
(on page C-
4) shows how these queues are structured with regard to the other registers.