Hardware
Copyright IXXAT Automation GmbH
171
IEM Manual, 1.5
7.3.4.1 SPI settings
On the Master, the following settings must be made:
Bit order :
MSB First
Data bits:
8 Bit
Clock polarity:
clock signal in idle is ‘0’
Clock phase:
data write on falling edge, data read on rising edge
Min. data rate:
5,0 MHz
Max. data rate:
12,5 MHz
IDLE
IDLE
Latch Shift
MSB
LSB
Figure 7-18: SPI settings
Note:
Please be sure that your SPI clock is in between of the minimum
and maximum data rate. Violating these requirements may result in
timeout errors.
7.3.4.2 Timing CS#
Figure 7-19: Timing CS#
Note:
Please be sure that the chip select (CS#) is on low level over the
whole time during the complete datagram read or write cycle.
SPI datagram
CS#
MISO/MOSI