Hardware
Copyright IXXAT Automation GmbH
170
IEM Manual, 1.5
7.3.3.4 Timing diagram
In Figure 7-16, the timing for accessing the DPRAM is displayed. An access to
the DPRAM will be initiated as soon as ext_cs_n and ext_wr_n respectively
ext_rd_n are active (T
1
starts). Exact timing for T
2
is not defined, but it is ad-
visable to have ext_wr_n and ext_rd_n not before ext_cs_n. The address, data
and byte enable signals have to be set at the same point of time as the
ext_rd_n and ext_wr_n signals.
ext_cs_n
ext_wr_n/
ext_rd_n
ext_addr/
ext_be_n
datain
T
2
T
3
T
4
T
5
T
6
T
10
T
7
dataout
T
8
T
9
T
11
T
1
Figure 7-16: Timing diagram DPRAM interface
In the table below, the detailed timing is specified.
Time Detail
Values
Remark
min
max
T1
write access time
40ns
T2
CS active to RD/WR active
0ns
T3
address/byte enable valid to RD/WR active
0ns
T4
data valid to write active
0ns
T5
read active to data out low-z
0ns
T6
read active to data out valid
80ns
T7
read inactive to data out high-z
15ns
T8
data hold from write end
0ns
T9
address/ byte enable hold from RD/WR end
0ns
T10
RD/WR inactive to CS inactive
0ns
T11
access end to start of new access
13,3ns
Figure 7-17: Timing parallel access
7.3.4 Timing for SPI based access
For the communication via SPI, the FPGA will act as SPI slave and the host
must act as SPI master.
