Hardware
Copyright IXXAT Automation GmbH
164
IEM Manual, 1.5
7.1.1.2.4
Chip select (CS#)
Enable communication with the IEM when low.
7.1.1.2.5
Read (RD#)
Enable data output on D0-D15 when low.
Note:
These pins are only supported in parallel interface mode.
7.1.1.2.6
Write (WR#)
Enable data input on D0-D15 when low.
Note:
These pins are only supported in parallel interface mode.
7.1.1.2.7
7.2.7 SPI (SPI_CLK, SPI_CS#, SPI_MOSI, SPI_MISO)
Lines responsible for the serial communication also called SPI
Note:
These pins are only supported in serial interface mode.
7.1.1.2.8
GPIOs from application processor
7.1.1.2.8.1 GPIO2NIOS1 - parallel interface/SPI access mode
This pin is used to select the bus operating mode between SPI and parallel
interface. If the GPIO2NIOS1 has a high level, the parallel interface mode is
chosen. With a low level on it, the module works in the SPI mode. The rising
edge of the reset signal selects the mode. The Figure 7-3 shows the minimum
timing requirements.
Figure 7-3: Timing diagram to activate DPRAM/SPI operating mode
Access
GPIO2NIOS
SPI
0 (low level)
DPRAM
1 (high level)
Table 7-1: Truth table - DPRAM/SPI access
Reset
t
min
=100ns
GPIO2NIOS1
t
min
=80ns