Hardware
Copyright IXXAT Automation GmbH
163
IEM Manual, 1.5
Note:
These pins are only supported in parallel interface mode
7.1.1.2.2
Byte enable lines (BE0# and BE1#)
Active low byte enable lines which specify the byte of the read/write access:
BE0#
BE1#
Access
Description
1
1
-
not valid
0
1
8 bit
access on low byte addressed by ADDR1
– ADDR13
1
0
8 bit
access on high byte addressed by ADDR1
– ADDR13
0
0
16 bit
16 bit access on word addressed by ADDR1
– ADDR13
Figure 7-2: Byte enable lines
Note:
These pins are only supported in parallel interface mode.
Example:
A 32 bit variable (0x1234ABCD) was stored into the Shared memory. The
byte-order is little endian and the value is stored at address offset 0x0000 of
the shared memory.
16-bit access (read/write)
BE0#
BE1#
A1
AD[15:8]
AD[7:0]
0
0
0
0xAB
0xCD
0
0
1
0x12
0x34
8-bit access (read/write)
BE0#
BE1#
A1
AD[15:8]
AD[7:0]
0
1
0
invalid
0xCD
1
0
0
0xAB
invalid
0
1
1
invalid
0x34
1
0
1
0x12
invalid
7.1.1.2.3
Data input/output (D0
– D15)
Data transfer pins dependent on the Pins ADDR1-ADDR13, BE0#, BE1#,
CS#, RD# and WR#. D0 is the least significant bit, D15 the most significant.
Note:
These pins are only supported in parallel interface mode.