Hardware
Copyright IXXAT Automation GmbH
165
IEM Manual, 1.5
7.1.1.2.8.2 GPIO2NIOS2
Input pin for general purpose notification. Not used in the current implementa-
tion and reserved for future use.
7.1.1.2.9
GPIOs to application processor
Output pins for general purpose notification, further details are described in the
protocol specific sections.
Figure 7-4: Timing diagram GPIO to application processor
Bus protocol
GPIO2HOST1
GPIO2HOST2
EtherCAT
Special synchronization mechanism
(SYNC0)
Cyclic data
Ethernet/IP
-
-
PROFINET
-
-
Powerlink
-
Table 7-2: Overview of GPIOs to application processor
Note:
GPIO2HOST1 is only supported in parallel interface mode.
7.1.1.2.10 Reset (RESET#)
Initiates a system reset when low. This line will be triggered from the API by
means of the function
Figure 7-5: Reset timing diagram
Note:
This reset is a logical reset it will be only resets the FPGA. The
FPGA firmware is only loaded at the power-on cycle.
Reset
t
min
=100ns
GPIO2HOSTx
t
max
=67ns