
4-1
CHAPTER 4
BUS PROTOCOL
This chapter describes the protocol followed by bus agents in a transaction’s six phases. The
phases are:
•
Arbitration Phase
•
Request Phase
•
Error Phase
•
Snoop Phase
•
Response Phase
•
Data Phase
4.1.
ARBITRATION PHASE
A bus agent must have bus ownership before it can initiate a transaction. If the agent is not the
bus owner, it enters the Arbitration Phase to obtain ownership. Once ownership is obtained, the
agent can enter the Request Phase and issue a transaction to the bus.
4.1.1.
Protocol Overview
The Pentium Pro processor bus arbitration protocol supports two classes of bus agents: symmet-
ric agents and priority agents.
The symmetric agents support fair, distributed arbitration using a round-robin algorithm. Each
symmetric agent has a unique Agent ID between zero and three assigned at reset. The algorithm
arranges the four symmetric agents in a circular order of priority: 0, 1, 2, 3, 0, 1, 2, etc. Each
symmetric agent also maintains a common Rotating ID that reflects the symmetric Agent ID of
the most recent bus owner. On every arbitration event, the symmetric agent with the highest pri-
ority becomes the symmetric owner. Note that the symmetric owner is not necessarily the overall
bus owner. The symmetric owner is allowed to enter the Request Phase provided no other action
of higher priority is preventing the use of the bus.
The priority agent(s) has higher priority than the symmetric owner. Once the priority agent ar-
bitrates for the bus, it prevents the symmetric owner from entering into a new Request Phase un-
less the new transaction is part of an ongoing bus locked operation. The priority agent is allowed
to enter the Request Phase provided no other action of higher priority is preventing the use of
the bus.
Pentium Pro processors are symmetric agents. The priority agent normally arbitrates on behalf
of the I/O and possibly memory subsystems.
Содержание Pentium Pro Family
Страница 17: ...1 Component Introduction ...
Страница 26: ...2 Pentium Pro Processor Architecture Overview ...
Страница 27: ......
Страница 36: ...3 Bus Overview ...
Страница 62: ...4 Bus Protocol ...
Страница 105: ...5 Bus Transactions and Operations ...
Страница 126: ...6 Range Registers ...
Страница 131: ...7 Cache Protocol ...
Страница 135: ...8 Data Integrity ...
Страница 148: ...9 Configuration ...
Страница 161: ...10 Pentium Pro Processor Test Access Port TAP ...
Страница 172: ...11 Electrical Specifications ...
Страница 201: ...12 GTL Interface Specification ...
Страница 229: ...13 3 3V Tolerant Signal Quality Specifications ...
Страница 233: ...14 Thermal Specifications ...
Страница 239: ...15 Mechanical Specifications ...
Страница 241: ...15 2 MECHANICAL SPECIFICATIONS s Figure 15 1 Package Dimensions Bottom View ...
Страница 252: ...16 Tools ...
Страница 260: ...16 8 TOOLS Figure 16 4 Generic MP System Layout for Debug Port Connection ...
Страница 264: ...17 OverDrive Processor Socket Specification ...
Страница 290: ...A Signals Reference ...
Страница 320: ...Index ...
Страница 328: ......