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12-15
GTL+ INTERFACE SPECIFICATION
12.2.2.1. OUTPUT DRIVER ACCEPTANCE CRITERIA
Although Section 12.1.4., “AC Parameters: Flight Time” describes ways of amending flight time
to a receiver when the edge rate is lower than the requirements shown in Table 12-5, or when
there is excessive ringing, it is still preferable to avoid slow edge rates or excessive ringing
through good driver and system design, hence the criteria presented in this section.
As mentioned in note 2 of the previous section, the criteria for acceptance of an output driver
relate to the edge rate and the signal quality for the Lo-to-Hi transition, and primarily to the sig-
nal quality for the Hi-to-Lo transition when the device, with its targeted package, is simulated
into the Ref8n network (Figure 12-15). The edge rate portion of the AC specification is a good
initial target, but is insufficient for guaranteeing acceptable performance.
Since Ref8N is not the worst case network, and is expected to be modeled without many real
system effects (e.g., inter-trace crosstalk, DC & AC losses), the required signal quality is slightly
different than that specified in Section 12.1.3., “System AC Parameters: Signal Quality” of this
document.
The signal quality criterion for an acceptable driver design is that the signals produced by the
driver (at its fastest corner) at all Ref8N receiver pads must remain outside of the shaded areas
shown in Figure 12-9. Simulations must be performed at both device and operating extremes:
fast process corner at high V
CC
and low temperature, and slow process corner at low V
CC
and
high temperature, for both the rising and falling edges. The clock frequency should be at the de-
sired maximum (e.g. 66.6 MHz, or higher), and the simulation results should be analyzed both
from a quiescent start (i.e., first cycle in a simulation), and when preceded by at least one previ-
ous transition (i.e. subsequent simulation cycles).
The boundaries of the keep-out area for the Lo-to-Hi transition are formed by a vertical line at
the start of the receiver setup window (a distance T
SU
’ from the next clock edge), an 0.3V/ns
ramp line passing through the intersection between the V
REF
+100 mV level (the 100 mV is as-
sumed extra noise) and the beginning of the setup window, a horizontal line at V
REF
+300 mV
(which covers 200 mV of specified overdrive, and the 100 mV margin for extra noise coupled
to the waveform), and finally a vertical line behind the Clock at THD’. The keep-out zone for
the Hi-to-Lo transition uses analogous boundaries in the other direction. Raising V
REF
by 100
mV is assumed to be equivalent to having 100 mV of extra noise coupled to the waveform giving
it more downward ringback, such coupled noise could come from a variety of sources such as
trace-to-trace PCB coupling.
T
SU
’ is the receiver‘s setup time plus board clock driver and clock distribution skew and jitter,
plus an additional number that is inherited from the driver’s internal timings (to be described
next). Since the I/O buffer designer will most likely be simulating the driver circuit alone, certain
delays that add to T
CO
, such as: on-chip clock phase shift, clock distribution skew, and jitter, plus
other data latch or JTAG delays would be missing. It is easier if these numbers are added to T
SU
,
yielding T
SU
’ making the driver simulation simpler. For example, assume T
SU
to be 2.8 ns, PCB
clock generation and distribution skew plus jitter to be 1 ns, and unmodeled delays in the driver
to be typically about 0.8 ns, this yields a total T
SU
’ = 4.6 ns.