Intel Pentium Pro Family, Руководство разработчика, Страница: 134 / 328

7-3
CACHE PROTOCOL
BRP (Bus Read Part-line). A Bus Read Part-line transaction indicates that a requesting agent
issued a Memory Read Transaction for less than a full cache line.
BLR (Bus Locked Read). A Bus Locked Read transaction indicates that a requesting agent is-
sued a bus locked Memory Read Transaction. For the Pentium Pro processor, this will be for <=
8 bytes.
BWL (Bus Write Line). A Bus Write Line transaction indicates that a requesting agent issued
a Memory Write Transaction for a full cache line. This transaction indicates that a requesting
agent intends to write back a Modified line or an I/O agent intends to write a line to memory.
BWP (Bus Write Part-line). A Bus Write Part-line transaction indicates that a requesting agent
issued a Memory Write Transaction for less than a full cache line.
BLW (Bus Locked Write). A Bus Locked Write transaction indicates that a requesting agent
issued a bus locked Memory Write Transaction. For the Pentium Pro processor, this will be for
<= 8 bytes.
BRIL (Bus Read Invalidate Line). A Bus Read Invalidate Line transaction indicates that a re-
questing agent issued a Memory (Read) Invalidate Transaction for a full cache line. The request-
ing agent has had a read miss and intends to modify this line when the line is returned.
BIL (Bus Invalidate Line). A Bus Invalidate Line transaction indicates that a requesting agent
issued a Memory (Read) Invalidate Transaction for 0 bytes. The requesting agent contains the
line in S state and intends to modify the line. In case of a race condition, the response for this
transaction can contain an implicit writeback.
Implicit Writeback: A Response to Another Transaction. An implicit writeback is not an in-
dependent bus transaction. It is a response to another transaction that requests the most up-to-
date data. When an external request hits a Modified line in the local cache or buffer, an implicit
writeback is performed to provide the Modified line and at the same time, update memory.
7.2.3. Naming Convention for Transactions
The memory-access transaction names and abbreviations contain up to six components as
follows:
1. B=Bus, I=Internal, or omitted
2. A=Any, CL=Cache Locked, L=[split] Locked
3. R= Read, W= Write
4. I=Invalidate, or omitted
5. C=Code, D=Data, or omitted
6. L=Line, P=Partial, or omitted
All cache state transitions with respect to Internal requests assume that the DEFER# signal sam-
pled in the Snoop Result Phase is inactive. If DEFER# is sampled active and HITM# is inactive,
then no cache state transition is made. If the transaction receives a deferred response, the actual
cache state transition by the receiver is made during the Snoop Result Phase of the deferred reply
transaction. Cache state transitions associated with “bus” requests ignore the DEFER# signal.