Intel Pentium Pro Family, Руководство разработчика, Страница: 204 / 328

12-3
GTL+ INTERFACE SPECIFICATION
NOTES:
1. This ±2% tolerance is in addition to the ±10% tolerance of V
TT
, and could be caused by such factors as
voltage divider inaccuracy.
2. Z
EFF
= Z
0
(nominal) / (1+Cd/Co)1/2
Z
0
= Nominal board impedance; recommended to be 65
Ω
±10%. Z
0
is a function of the trace cross-sec-
tion, the distance to the reference plane(s), the dielectric constant,
ε
r, o f th e P C B m a te ria l a n d th e d ie le c -
tric c o n s ta n t o f t h e s o ld e r-m a s k / a ir fo r m ic ro -s t rip tra c e s .
Co = Total intrinsic nominal trace capacitance between the first and last bus agents, excluding the termi-
nation resistor tails. Co is a function of Z
0
and
ε
r. F o r Z 0
= 65
Ω
and
ε
r = 4 . 3 , C o is a p p ro x im a te ly 2 .6 6 p F / in
tim e s t h e n e tw o rk le n g th (firs t a g e n t to la s t a g e n t).
Cd = Sum of the Capacitance of all devices and PCB stubs (if any) attached to the net,
= PCB Stub CapacSocket CapacPackage Stub CapacDie Capacitance.
3. To reduce cost, a system would usually employ one value of R
T
for all its GTL+ nets, irrespective of the
Z
EFF
of individual nets. The designer may start with the average value of Z
EFF
in the system. The value of
R
T
may be adjusted to balance the Hi-to-Lo and Lo-to-Hi noise margins. Increasing the value of R
T
tends
to slow the rising edge, increasing rising flight time, decreasing the Lo-to-Hi noise margin, and increasing
the Hi-to-Lo noise margin by lowering V
OL
. R
T
can be decreased for the opposite effects.
R
T
affects GTL+ rising edge rates and the “apparent clock-to-out” time of a driver in a net as follows: A
large R
T
causes the standing current in the net to be low when the (open drain) driver is low (on). As the
driver switches off, the small current is turned off, launching a relatively small positive-going wave down
the net. After a few trips back and forth between the driver and the terminations (undergoing reflections at
intervening agents in the meantime) the net voltage finally climbs to V
TT
. Because the wave launched ini-
tially is relatively small in amplitude (than it would have been had R
T
been smaller and the standing cur-
rent larger), the overall rising edge climbs toward V
TT
at a slower rate. Notice that this effect causes an
increase in flight time, and has no influence on the true clock-to-out timing of the driver into the standard
25
Ω
test load.
4. Z
EFF
of all 8-load nets must remain between 45-65
Ω
under all conditions, including variations in Z
0
, Cd,
temperature, V
CC
, etc.
Table 12-1. System DC Parameters
Symbol Parameter Value Tolerance Notes
V
TT
Termination Voltage 1.5V
±
10%
V
REF
Input Reference Voltage 2/3 V
TT
±
2%
1
R
T
Termination Resistance Z
EFF
(nominal) See Note
2, 3
Z
EFF
Effective (Loaded) Network Impedance 45-65
Ω
4