Intel Pentium Pro Family, Руководство разработчика, Страница: 291 / 328

A-1
APPENDIX A
SIGNALS REFERENCE
This appendix provides an alphabetical listing of all Pentium Pro processor signals. The tables
at the end of this appendix summarize the signals by direction: output, input, and I/O.
A.1. ALPHABETICAL SIGNALS REFERENCE
A.1.1. A[35:3]# (I/O)
The A[35:3]# signals are the address signals. They are driven during the two-clock Request
Phase by the request initiator. The signals in the two clocks are referenced Aa[35:3]# and
Ab[35:3]#. During both clocks, A[35:24]# signals are protected with the AP1# parity signal, and
A[23:3]# signals are protected with the AP0# parity signal.
The Aa[35:3]# signals are interpreted based on information carried during the first Request
Phase clock on the REQa[4:0]# signals.
For memory transactions as defined by REQa[4:0]# = {XX01X,XX10X,XX11X}, the
Aa[35:3]# signals define a 2
36
-byte physical memory address space. The cacheable agents in the
system observe the Aa[35:3]# signals and begin an internal snoop. The memory agents in the
system observe the Aa[35:3]# signals and begin address decode to determine if they are respon-
sible for the transaction completion. Aa[4:3]# signals define the critical word, the first data
chunk to be transferred on the data bus. Cache line transactions use the burst order described in
Section 3.3.4.1., ‘Line Transfers” to transfer the remaining three data chunks.
For Pentium Pro processor IO transactions as defined by REQa[4:0]# = 1000X, the signals
Aa[16:3]# define a 64K+3 byte physical IO space. The IO agents in the system observe the sig-
nals and begin address decode to determine if they are responsible for the transaction comple-
tion. Aa[35:17]# are always zero. Aa16# is zero unless the IO space being accessed is the first
three bytes of a 64KByte address range.
For deferred reply transactions as defined by REQa[4:0]# = 00000, Aa[23:16]# carry the de-
ferred ID. This signal is the same deferred ID supplied by the request initiator of the original
transaction on Ab[23:16]#/DID[7:0]# signals. Pentium Pro processor bus agents that support de-
ferred replies sample the deferred ID and perform an internal match against any outstanding
transactions waiting for deferred replies. During a deferred reply, Aa[35:24]# and Aa[15:3]# are
reserved.
For the branch-trace message transaction as defined by REQa[4:0]# = 01001 and for special and
interrupt acknowledge transactions, as defined by REQa[4:0]# = 01000, the Aa[35:3]# signals
are reserved and undefined.