Intel Pentium II, Руководство разработчика

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E
TEST ACCESS PORT (TAP)
6-7
8/26/97 1:10 PM CH06.DOC
INTEL CONFIDENTIAL
(until publication date)
6.3. INSTRUCTION SET
Table 6-1 contains descriptions of the encoding and operation of the TAP instructions. There
are seven 1149.1-defined instructions implemented in the TAP. These instructions select
from among four different TAP data registers — the boundary scan, BIST result, device ID,
and bypass registers.
Table 6-1. 1149.1 Instructions in the Processor TAP
Action During:
TAP
Instruction Opcode
Processor
Pins Drive
From:
Data
Register
Selected RT/Idle Capture-DR Shift-DR Update-DR
EXTEST 000000 Boundary
scan Boundary
scan — Sample all
processor
pins Shift data
register Update data
register
SAMPLE/
PRELOAD 000001 — Boundary
scan — Sample all
processor
pins Shift data
register Update data
register
IDCODE 000010 — Device ID — Load unique
processor ID
code Shift data
register —
CLAMP 000100 Boundary
scan Bypass — Reset bypass
reg Shift data
register —
RUNBIST 000111 Boundary
scan BIST
result BIST
starts
1
Capture BIST
result Shift data
register —
HIGHZ 001000 Floated Bypass — Reset bypass
reg Shift data
register —
BYPASS 111111 — Bypass — Reset bypass
reg Shift data
register —
Reserved All other Reserved Reserved Reserved Reserved Reserved Reserved
NOTE:
1. The processor must be reset after this command.
TAP instructions in the P6 family are 6 bits long. For each listed instruction, the table shows
the instruction’s encoding, what happens on the processor pins, which TAP data register is
selected by the instruction, and the actions which occur in the selected data register in each
of the controller states. A single hyphen indicates that no action is taken. Note that not all of
the TAP data registers have a latched parallel output (i.e., some are only simple shift
registers). For these data registers, nothing happens during the Update-DR controller state.
Full details of the operation of these instructions can be found in the 1149.1 standard.
The only TAP instruction which does not operate exactly as defined in the 1149.1 standard is
RUNBIST. In the 1149.1 specification, Rule 7.9.1(b) states that: “Self-test mode(s) of
operation accessed through the RUNBIST instruction shall execute only in the Run-Test/Idle