Intel Pentium II, Руководство разработчика

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E
MICRO-ARCHITECTURE OVERVIEW
2-3
8/26/97 10:42 AM CH02.DOC
INTEL CONFIDENTIAL
(until publication date)
2.2. THE PENTIUM
®
II PROCESSOR PIPELINE
In order to get a closer look at how the P6 family micro-architecture implements Dynamic
Execution, Figure 2-3 shows a block diagram of the Pentium II processor with cache and
memory interfaces. The “Units” shown in Figure 2 represent stages of the Pentium II
processor pipeline.
Instruction Pool
L1 ICache L1 DCache
Bus Interface Unit
L2 Cache
System Bus
Fetch Load
Store
Fetch/
Decode
Unit
Dispatch/
Execute
Unit
Retire
Unit
000926
Figure 2-3. The Three Core Engines Interface with Memory via Unified Caches
•
The FETCH/DECODE unit: An in-order unit that takes as input the user program
instruction stream from the instruction cache, and decodes them into a series of
µoperations (µops) that represent the dataflow of that instruction stream. The pre-fetch is
speculative.
•
The DISPATCH/EXECUTE unit: An out-of-order unit that accepts the dataflow stream,
schedules execution of the µops subject to data dependencies and resource availability
and temporarily stores the results of these speculative executions.