Intel Pentium II, Руководство разработчика

Страница: 19 / 226

E
2-1
8/26/97 10:42 AM CH02.DOC
INTEL CONFIDENTIAL
(until publication date)
CHAPTER 2
MICRO-ARCHITECTURE OVERVIEW
The Pentium II processor uses the same dynamic execution micro-architecture as the other
members of P6 family of Intel Architecture processors. This three-way superscalar, pipelined
micro-architecture features a decoupled, multi-stage superpipeline, which trades less work
per pipestage for more stages. The Pentium II processor, for example, has twelve stages with
a pipestage time 33 percent less than the Pentium processor, which helps achieve a higher
clock rate on any given manufacturing process.
The approach used in the P6 family micro-architecture removes the constraint of linear
instruction sequencing between the traditional “fetch” and “execute” phases, and opens up a
wide instruction window using an instruction pool. This approach allows the “execute” phase
of the processor to have much more visibility into the program instruction stream so that
better scheduling may take place. It requires the instruction “fetch/decode” phase of the
processor to be much more efficient in terms of predicting program flow. Optimized
scheduling requires the fundamental “execute” phase to be replaced by decoupled
“dispatch/execute” and “retire” phases. This allows instructions to be started in any order but
always be completed in the original program order. Processors in the P6 family may be
thought of as three independent engines coupled with an instruction pool as shown in
Figure 2-1.
Fetch/
Decode
Unit
Dispatch/
Execute
Unit
Retire
Unit
Instruction Pool
000925
Figure 2-1. Three Engines Communicating Using an Instruction Pool