Intel Pentium II, Руководство разработчика

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GTL+ INTERFACE SPECIFICATIONS
E
8-12
8/28/97 10:31 AM CH08.DOC
INTEL CONFIDENTIAL
(until publication date)
The maximum acceptable Flight Time is determined on a net-by-net basis, and is usually
different for each unique driver-receiver pair. The maximum acceptable Flight Time can be
calculated using the following equation (known as the setup time equation):
T
FLIGHT_MAX
= Clock Period - T
CO-MAX
- T
SU-MIN
- T
CLK_SKEW-MAX
- T
CLK_JITTER-MAX
- CLK
ADJ
- T
ADJ
Where:
T
CO-MAX
is the maximum clock-to-out delay of a driving agent,
T
SU-MIN
is the minimum setup time required by a receiver on the same net,
T
CLK_SKEW-MAX
is the maximum anticipated time difference between the driver’s and
the receiver’s clock inputs, and
T
CLK_JITTER-MAX
is maximum anticipated edge-to-edge phase jitter.
CLK
ADJ
is the host clock adjustment factor.
T
ADJ
- an empirical timing adjustment factor that accounts for timing “pushout” seen
when multiple bits change state at the same time. The factors that contribute to the
adjustment factor include crosstalk on the PCB, substrate, and packages,
simultaneous switching noise, and edge rate degradation caused by inductance in the
ground return path.
The above equation should be checked for all pairs of devices on all nets of a bus.
The minimum acceptable Flight Time is determined by the following equation (known as the
hold time equation):
T
FLIGHT_MIN
= T
HOLD
+ CLK
SKEW
+ CLK
ADJ
- T
CO_MIN
Where:
T
CO-MIN
—the minimum clock to output specification.
T
FLT-MIN
—the minimum flight time.
T
HOLD
—the minimum specified input hold time.
CLK
SKEW
—the maximum variation between components receiving the same clock edge.
CLK
ADJ
—the host clock adjustment factor.
The Hold time equation is independent of clock jitter, since data is released by the driver and
is required to be held at the receiver on the same clock edge.