Intel NetStructure ZT 5085, Руководство пользователя

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Technical Product Specification
Specifications
A.7.2 CMM Slot P2 Interface
Table 33 specifies the P2 interface for CMM slots .
1
A.7.3 CMM Slot P3 Interface
Table 35 specifies the P3 interface for CMM slots.
Table 33. P2 Connector CMM Pin Assignments
Pin # Z A B C D E F
11 GND N_SCL1
1
N_SDA1
1
N_SCL10
2
N_SDA10
2
N_SCL18
2
GND
10 GND N_SCL2
2
N_SDA2
2
N_SCL11
2
N_SDA11
2
N_SDA18
2
GND
9 GND N_SCL3
2
N_SDA3
2
N_SCL12
2
N_SDA12
2
N_SCL19
2
GND
8 GND N_SCL4
2
N_SDA4
2
N_SCL13
2
N_SDA13
2
N_SDA19
2
GND
7 GND N_SCL5
2
N_SDA5
2
N_SCL14
2
N_SDA14
2
N_SCL20
2
GND
6 GND N_SCL6
2
N_SDA6
2
N_SCL15
2
N_SDA15
2
N_SDA20
2
GND
5 GND N_SCL7
2
N_SDA7
2
N_SCL16
2
N_SDA16
2
N_SCL21
2
GND
4 GND N_SCL8
2
N_SDA8
2
N_SCL17
2
N_SDA17
2
N_SDA21
2
GND
3 GND N_SCL9
2
N_SDA9
2
GND NEG_O HLY_O# GND
2 GND R_SCL IPMB_PWR
3
RES IPMB_PWR
3
HLY_I# GND
1 GND GND R_SDA CMM_SEL# NEG_I GND GND
1. In the ZT 5085 midplane, N_SCL1 and N_SDA1 signals are not used because the CMMs are in slot 1.
2. The CompactPCI* specifications define the IPMB signals as bused. Intel systems that implement CMM
slots route slot-specific IPMBs to the CMM(s) in a star topology. The IPMB in slot n is connected to the
N_SCLn and N_SDAn signals on the CMM(s).
Table 35. P3 Connector CMM Pin Assignments (Sheet 1 of 2)
Pin # Z A B C D E F
11 GND N_HLY1#
1
N_BDS1#
1
N_HLY10#
2
N_BDS10#
3
N_HLY18#
2
GND
10 GND N_HLY2#
2
N_BDS2#
3
N_HLY11#
2
N_BDS11#
3
N_BDS18#
3
GND
9 GND N_HLY3#
2
N_BDS3#
3
N_HLY12#
2
N_BDS12#
3
N_HLY19#
2
GND
8 GND N_HLY4#
2
N_BDS4#
3
N_HLY13#
2
N_BDS13#
3
N_BDS19#
3
GND
7 GND N_HLY5#
2
N_BDS5#
3
N_HLY14#
2
N_BDS14#
3
N_HLY20#
2
GND
6 GND N_HLY6#
2
N_BDS6#
3
N_HLY15#
2
N_BDS15#
3
N_BDS20#
3
GND
5 GND N_HLY7#
2
N_BDS7#
3
N_HLY16#
2
N_BDS16#
3
N_HLY21#
2
GND
4 GND N_HLY8#
2
N_BDS8#
3
N_HLY17#
2
N_BDS17#
3
N_BDS21#
3
GND
3 GND N_HLY9#
2
N_BDS9#
3
IPMB_PWR RES RES GND
2 GND RES GND RES GND RES GND
1 GND IPMB_PWR RES PRES_O# RES IPMB_PWR GND