88
Technical Product Specification
Specifications
Boards that do not implement H.110 and do not have a J4 connector may be installed in H.110
slots. In this case, the J5/P5 interface may be used for rear panel I/O. Note, however, that the H.110
P5 connector has pin staging and that the ‘Z’ GND pins are not populated in the midplane
connector.
specifies the P5 interface for the H.110 slots. This is in accordance with the PICMG 2.5
R1.0 specification. Refer to the PICMG specification for more detail.
A.6.7
P4/P5 Rear Panel I/O Interface
This section defines the P4/P5 interface for non-fabric slots.
The P4 and P5 interfaces for non-fabric slots are available for any board-specific rear panel I/O.
The midplane does not connect to these signals, except to ground the Z and F columns of pins.
Table 31. H.110 P5 Pin Assignments
Pin #
A
B
C
D
E
F
22
T1
T9
T17
T25
IN/C
[No Pin]
21
R1
R9
R17
R25
IN/C
[No Pin]
20
T2
T10
T18
T26
IN/C
[No Pin]
19
R2
R10
R18
R26
IN/C
[No Pin]
18
T3
T11
T19
T27
IN/C
[No Pin]
17
R3
R11
R19
R27
IN/C
[No Pin]
16
T4
T12
T20
T28
IN/C
[No Pin]
15
R4
R12
R20
R28
IN/C
[No Pin]
14
T5
T13
T21
T29
IN/C
[No Pin]
13
R5
R13
R21
R29
IN/C
[No Pin]
12
T6
T14
T22
T30
IN/C
[No Pin]
11
R6
R14
R22
R30
IN/C
[No Pin]
10
T7
T15
T23
T31
IN/C
[No Pin]
9
R7
R15
R23
R31
IN/C
[No Pin]
8
T8
T16
T24
T32
IN/C
[No Pin]
7
R8
R16
R24
R32
IN/C
[No Pin]
6
IN/C
IN/C
IN/C
IN/C
IN/C
[No Pin]
5
IN/C
IN/C
IN/C
IN/C
IN/C
[No Pin]
4
Uo0
Uo1
GND_FT
GND_FT
GND_FT
[No Pin]
3
Ui0
Ui1
Uo4
Uo5
Uo6
[No Pin]
2
Uo2
Uo3
Ui4
Ui5
Ui6
[No Pin]
1
Ui2
Ui3
+5V_FT
+12V_FT
-12V_FT
[No Pin]
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