12. Register Descriptions
320
PowerSpan II User Manual
80A1010_MA001_09
Integrated Device Technology
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Px_LOCKOUT:
When set, all configuration and memory register space accesses from PCI are retried.
The Px_LOCKOUT bit must be cleared for all memory space accesses to the PowerSpan II’s PCI
target images.
The Px_LOCKOUT bit must be cleared before the corresponding PCI Target Image claims a
transaction. The bit is cleared by an agent on the Processor Bus or by EEPROM load. The bit is cleared
automatically by PowerSpan II when the PWRUP_BOOT option is set to PCI.
PCI_ARB_CFG
: When set, this bit enables recognition of external master requests on
PCI_REQ#[7:5]. The user must set this bit after completing configuration all of the PowerSpan II
floating PCI arbitration pins with bits PCI_M7, PCI_M6 and PCI_M5. When PCI_ARB_CFG is not
set, requests from external masters connected to PCI_REQ#[7:5] are ignored.
Initialization of PCI_ARB_CFG is not required for the Single PCI PowerSpan II because
PCI_REQ#[7:5]/PCI_GNT#[7:5] are dedicated to the PCI-1 Interface.
PCI_Mx: Each of these PCI Master bits must be explicitly initialized by the user to indicate which
PowerSpan II PCI arbiter should service the pair of PCI_REQ#/PCI_GNT# pins. Initialization occurs
through EEPROM load or a register write.
indicates register bit to arbitration pin mappings:
The PCI_Mx bits do not affect the behavior of the Single PCI PowerSpan II because
PCI_REQ#[7:5]#/PCI_GNT#[7:5] are dedicated to the PCI-1 Interface.
PCI_M5
R/W
G_RST
0
EEPROM
PCI Arbiter Master 5
0=PowerSpan II PCI-1 arbiter
1=PowerSpan II PCI-2 arbiter
Single PCI PowerSpan II: Reserved
PowerSpan II does not terminate the cycle when the Px_LOCKOUT bit is not cleared during
a memory space access to the PCI target images. If PowerSpan II does not terminate the
cycle, the PCI bus experiences a deadlock condition.
Table 80: Arbitration Pin Mappings
Bit
Arbitration Pins
PCI_M5
PCI_REQ#[5]/PCI_GNT#[5]
PCI_M6
PCI_REQ#[6]/PCI_GNT#[6]
PCI_M7
PCI_REQ#[7]/PCI_GNT#[7]
Name
Type
Reset
By
Reset
State
Function
Содержание PowerSpan II
Страница 8: ...Contents 8 PowerSpan II User Manual 80A1010_MA001_09 Integrated Device Technology www idt com ...
Страница 14: ...List of Tables 14 PowerSpan II User Manual 80A1010_MA001_09 Integrated Device Technology www idt com ...
Страница 18: ...About this Document 18 PowerSpan II User Manual 80A1010_MA001_09 Integrated Device Technology www idt com ...
Страница 82: ...2 PCI Interface 82 PowerSpan II User Manual 80A1010_MA001_09 Integrated Device Technology www idt com ...
Страница 112: ...3 Processor Bus Interface 112 PowerSpan II User Manual 80A1010_MA001_09 Integrated Device Technology www idt com ...
Страница 156: ...7 Interrupt Handling 156 PowerSpan II User Manual 80A1010_MA001_09 Integrated Device Technology www idt com ...
Страница 380: ...12 Register Descriptions 380 PowerSpan II User Manual 80A1010_MA001_09 Integrated Device Technology www idt com ...
Страница 394: ...14 Package Information 394 PowerSpan II User Manual 80A1010_MA001_09 Integrated Device Technology www idt com ...
Страница 414: ...15 AC Timing 414 PowerSpan II User Manual 80A1010_MA001_09 Integrated Device Technology www idt com ...
Страница 416: ...16 Ordering Information 416 PowerSpan II User Manual 80A1010_MA001_09 Integrated Device Technology www idt com ...
Страница 420: ...A Hardware Implementation 420 PowerSpan II User Manual 80A1010_MA001_09 Integrated Device Technology www idt com ...
Страница 428: ...B Typical Applications 428 PowerSpan II User Manual 80A1010_MA001_09 Integrated Device Technology www idt com ...
Страница 432: ...Glossary 432 PowerSpan II User Manual 80A1010_MA001_09 Integrated Device Technology www idt com ...