IDT PowerSpan II, Руководство пользователя

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15. AC Timing 397
PowerSpan II User Manual
80A1010_MA001_09
Integrated Device Technology
www.idt.com
1. Pulse width measured from Vdd Core (2.5V), Vdd I/O (3.3V), and Px_VDDA supplies in specification
2. Required for PB_CLK, and P1_CLK. This parameter ensures that each PLL locks. If a frequency change is required, a new power-up sequence
must be initiated.
3. This parameter is a function of the slowest frequency of PB_CLK, and P1_CLK. The minimum occurs at 100 MHz, the maximum at 25 MHz.
After this time, PowerSpan II is synchronized to external buses and able to participate in transactions once externally applied resets are released.
4. Assertion of TRST_ is required at power-up to initialize the JTAG controller and configure the Boundary Scan Register for normal system oper-
ation.
5. The maximum specification ensures correct power-up levels on PB_FAST, and P1_M66EN and ensures stable system levels on INT[5:1]_ before
the power-up reset sequence completes. The INT[4]_ signal has a minimum time of 3.2.
6. The ratio of largest to smallest clock period for PB_CLK, P1_CLK must be strictly less than four. For example, if PB_CLK period is 12 ns, the
period of P1_CLK must be less than 48 ns.
t
124
PB_CLK cycle to cycle jitter 300 ps
PCI Clock Timing
t
130
P1_CLK period 15 40 ns
P1_CLK frequency 25 66 MHz
t
131
P1_CLK high time 6 ns
t
132
P1_CLK low time 6 ns
t
133
P1_CLK slew rate 2 V/ns
t
134
P1_CLK cycle to cycle jitter 300 ps
Clock to Clock Relationships
t
140
Clock period ratio 1 < 4 - 6
Table 97: Reset, and Clock Timing Parameters
Timing
Parameter Description
CE/IE
Units Note Min Max