IDT 89HPES12N3, Руководство пользователя

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IDT Switch Operation Switch Time-Outs
PES12N3 User Manual 4 - 5 June 7, 2006
Notes
root; increments the End-to-End Parity Error Count (EEPERRC) field in the SWSIPECNT register associ-
ated with the port on which the error was detected; and sets the Detected Parity Error (DPE) bit in the
PCISTS register if the error was detected by a downstream port or sets DPE bit in the PCI Secondary
Status (SECSTS) register if the error was detected by an upstream port.
To prevent error flooding, error messages are not sent to the root once the EEPERRC field saturates.
Since PCI Express switches do not normally generate ERR_NONFATAL messages, the Silent End-to-End
Parity Checking bit (SEEPC) bit in the SWSICTL register is provided to disable generation of error
messages and setting of the Detected Parity Error bit when internal corruption is detected.
The default state of the switch following a fundamental reset is to enable this error reporting. (Note that
the Device Control register in the PCI Express capability structure also has a bit that enables generation of
ERR_NONFATAL messages and that the default value of this bit is to disable these messages.)
In addition to TLPs that flow through the switch, cases exist in which TLPs are produced and consumed
by the switch (e.g., a configuration requests and responses). Whenever a TLP is produced by the switch,
parity is computed as the TLP is generated. Thus, error protection is provided on produced TLPs as they
flow through the switch. In addition, parity is checked on all consumed TLPs. If an error is detected, the TLP
is discarded and an error is reported using the mechanism described above.
This means that a parity error reported at a switch port cannot be definitively used to identify the location
at which the error occurred as the error may have occurred when parity as generated at another port, in the
switch core, or may have been generated locally (i.e., for ingress TLPs to the switch core which are
consumed by the port such as Type 0 configuration read requests on the root port).
Switch Time-Outs
The switch discards any TLP that reaches the head of an input buffer and is more than 50ms old.
For non-posted and completion TLPs, the requester’s completion time-out mechanism will detect
discarded TLPs. No similar mechanism exists in PCIe for posted TLPs. Therefore, whenever a posted TLP
is discarded by the switch due to a time-out, an error non-fatal (ERR_NONFATAL) message (if this
message reporting is enabled) is sent to the root.
Whenever a TLP is discarded from a posted input buffer, the Posted TLP Time-out Count (PTLPTOC)
field is incremented in the Switch System Integrity Time-Out Drop Count (SWSITDCNT) register in the port
on which the TLP was received. This is a saturating counter that is automatically cleared when read. When-
ever a TLP is discarded from a non-posted input buffer, the Non-Posted TLP Time-out Count (NPTLPTOC)
field is incremented in this register and whenever a TLP is discarded from a completion input buffer, the
Completion TLP Time-out Count (NPTLPTOC) field is incremented.
To prevent error flooding, error messages are not sent to the root once the PTLPTOC counter saturates.
Since PCI Express switches do not normally generate ERR_NONFATAL messages, the Silent Posted TLP
Time-out (SPTLPTO) bit in the SWSICTL register is provided to disable generation of error non-fatal
messages. When this bit is set, ERR_NONFATAL messages are not generated when posted transactions
received on the corresponding port are discarded. The PTLPTOC field however is always updated.
Locking
The PES12N3 supports locked transactions, allowing legacy software to run without modification on
PCIe. Only one locked transaction sequence may be in progress at a time. A locked transaction sequence
is requested by the root by issuing a Memory Read Request - Locked (MRdLk) transaction. A lock is estab-
lished when a lock request is successfully completed with a Completion with Data - Locked (CplDLk). A lock
is released with an Unlock message (Msg).