IDT 89HPES12N3, Руководство пользователя

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IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition
PES12N3 User Manual 9 - 29 June 7, 2006
Notes
PCIEDSTS - PCI Express Device Status (0x04A)
8 ETFEN RW 0x0 Extended Tag Field Enable. Since the transparent bridge
never generates a transaction that requires a completion,
this bit has no functional effect on the device during normal
operation.
9 PFEN RO 0x0 Phantom Function Enable. The bridge does not support
phantom function numbers. Therefore, this field is hard-
wired to zero.
10 AUXPMEN RO 0x0 Auxiliary Power PM Enable. The device does not imple-
ment this capability.
11 ENS RO 0x0 Enable No Snoop. The transparent bridge does not gener-
ate transactions with the No Snoop bit set and passes
transactions through the bridge with the No Snoop bit
unmodified. Therefore, this field has no functional effect on
the behavior of the transparent bridge.
14:12 MRRS RO 0x0 Maximum Read Request Size. The transparent bridge
does not generate transactions larger than 128 bytes and
passes transactions through the bridge with the size
unmodified. Therefore, this field has no functional effect on
the behavior of the transparent bridge.
15 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
0 CED RW1C 0x0 Correctable Error Detected. This bit indicates the status
of correctable errors. Errors are logged in this register
regardless of whether error reporting is enabled or not.
1 NFED RW1C 0x0 Non-Fatal Error Detected. This bit indicates the status of
correctable errors. Errors are logged in this register regard-
less of whether error reporting is enabled or not.
2 FED RW1C 0x0 Fatal Error Detected. This bit indicates the status of Fatal
errors. Errors are logged in this registers regardless of
whether error reporting is enabled or not.
3 URD RW1C 0x0 Unsupported Request Detected. This bit indicates the
device received an Unsupported Request. Errors are
logged in this register regardless of whether error reporting
is enabled or not.
4 AUXPD RO 0x0 Aux Power Detected. Devices that require AUX power,
set this bit when AUX power is detected.This device does
not require AUX power, hence the value is hardwired to
zero.
5 TP RO 0x0 Transactions Pending. The transparent bridge does not
issue Non-Posted Requests on its own behalf. Therefore,
this field is hardwired to zero.
15:6 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description