IDT Switch Operation
Switch Core Errors
PES12N3 User Manual
4 - 9
June 7, 2006
Notes
–
Reception of TLPs that have no route (i.e., do not match an address or ID route through the
switch). TLPs that have no route should be treated as unsupported requests.
–
Reception of a TLP destined to a disabled downstream port (link down or MAE/IOAE bit cleared
in PA_PCICMD register). TLPs destined to a disabled downstream port should be treated as
unsupported requests.
–
Reception of a TLP that matches a VGA region and the VGA Enable (VGAEN) bit is set in the
upstream port but the TLP does not map to either downstream port (i.e., VGAEN is cleared in both
downstream ports and the transaction does not map to any of the base/limit pairs associated with
the downstream ports).
The following events received by the switch core from the downstream ports are treated as Unsupported
Requests (UR) and for non-posted transactions, result in a Unsupported Request (UR) completion to be
returned to the port on which the TLP was received.
–
Reception of Msg or MsgD TLPs with route by address routing prior to initialization of the PCI-PCI
bridge. Prior to initialization of the PCI-PCI bridge, no transactions should be routed to the switch
core.
–
Reception of Msg or MsgD TLPs with route by ID to the PCI-PCI bridge primary bus number after
bus enumeration has completed. There are no entities that generate accept messages on the
virtual PCI bus within the switch (i.e., the primary bus number).
–
Reception of route by address TLPs whose address matches an upstream port’s memory or I/O
base/limit pair and does not match a downstream ports’ memory or I/O base/limit pair. TLPs that
have no route (i.e., not destined for any upstream or downstream port) should be treated as
unsupported requests.
–
Reception of TLPs that have no route (i.e., do not match an address or ID route through the
switch). TLPs that have no route should be treated as unsupported requests.
–
Reception of any configuration TLP. Configuration requests can only be generated by the root and
received on the upstream port.
–
Reception of a route by ID TLP to a port that has its primary bus number set to its secondary bus
number. Such a port is uninitialized.
–
Reception of a TLP that utilizes implicit routing - broadcast from root. Such a TLP can only be
received by the upstream port.
–
Reception of a TLP that matches a VGA region in a downstream port when the downstream port’s
VGA Enable (VGAEN) bit is set in its Bridge Control (BCTRL) register.
–
Reception of a TLP destined to a disabled downstream port (link down or MAE/IOAE bit cleared
in PCICMD register) or the upstream port when the Bus Master Enable (BME) bit is not set in the
PCICMD register. TLPs destined to a disabled downstream port should be treated as unsupported
requests.
Содержание 89HPES12N3
Страница 10: ...IDT Table of Contents PES12N3 User Manual iv June 7 2006 Notes...
Страница 14: ...IDT List of Figures PES12N3 User Manual viii June 7 2006 Notes...
Страница 36: ...IDT Clocking Reset and Initialization Reset PES12N3 User Manual 2 8 June 7 2006 Notes...
Страница 40: ...IDT Link Operation Slot Power Limit Support PES12N3 User Manual 3 4 June 7 2006 Notes...
Страница 50: ...IDT Switch Operation Switch Core Errors PES12N3 User Manual 4 10 June 7 2006 Notes...
Страница 54: ...IDT Power Management Active State Power Management PES12N3 User Manual 5 4 June 7 2006 Notes...
Страница 62: ...IDT Hot Plug and Hot Swap Hot Swap PES12N3 User Manual 6 8 June 7 2006 Notes...
Страница 78: ...IDT SMBus Interfaces Slave SMBus Interface PES12N3 User Manual 7 16 June 7 2006 Notes...
Страница 142: ...IDT Transparent Mode Operation Generic PCI to PCI Bridge Register Definition PES12N3 User Manual 9 62 June 7 2006 Notes...
Страница 148: ...IDT Test and Debug SerDes Test Clock PES12N3 User Manual 10 6 June 7 2006...
Страница 158: ...IDT JTAG Boundary Scan Usage Considerations PES12N3 User Manual 11 10 June 7 2006 Notes...